Altera 100G Development Kit, Stratix IV GT Edition Uživatelský manuál stáhnout pdf (Strana 57)

Chapter 2: Board Components 2–49

Components and Interfaces

September 2010 Altera Corporation 100G Development Kit, Stratix IV GT Edition Reference Manual

f For more information about the memory interfaces, refer to the External Memory

Interface Handbook.

DDR3 Interface

The DDR3 interface consists of eight DDR3 devices, each providing a 64-MB interface

with a 16-bit data bus.

Table 2–37 lists the pin assignments for the DDR3 interface and their corresponding

schematic signal names and Stratix IV GT pin numbers.

Table 2–37. DDR3 Interface Pin Assignments, Schematic Signal Names, and Functions (Part 1 of 8)

Board Reference Description

Schematic

Signal Name

Stratix IV GT

Device

Pin Name

Other

Connections

DDR3A Interface

U36.N3, U37.N3 Address bus

DDR3A_A0

U44.C19 —

U36.P7, U37.P7 Address bus

DDR3A_A1

U44.T23 —

U36.P3, U37.P3 Address bus

DDR3A_A2

U44.D21 —

U36.N2, U37.N2 Address bus

DDR3A_A3

U44.D20 —

U36.P8, U37.P8 Address bus

DDR3A_A4

U44.L16 —

U36.P2, U37.P2 Address bus

DDR3A_A5

U44.C20 —

U36.R8, U37.R8 Address bus

DDR3A_A6

U44.P19 —

U36.R2, U37.R2 Address bus

DDR3A_A7

U44.D22 —

U36.T8, U37.T8 Address bus

DDR3A_A8

U44.R18 —

U36.R3, U37.R3 Address bus

DDR3A_A9

U44.C22 —

U36.L7, U37.L7 Address bus

DDR3A_A10

U44.J25 —

U36.R7, U37.R7 Address bus

DDR3A_A11

U44.M25 —

U36.N7, U37.N7 Address bus

DDR3A_A12

U44.K20 —

U36.M2, U37.M2 Bank address bus

DDR3A_BA0

U44.D19 —

U36.N8, U37.N8 Bank address bus

DDR3A_BA1

U44.R24 —

U36.M3, U37.M3 Bank address bus

DDR3A_BA2

U44.C18 —

U36.K3, U37.K3 Column address select

DDR3A_CASN

U44.J24 —

U36.K7, U37.K7 Clock input N

DDR3A_CK_N

U44.D23 —

U36.J7, U37.J7 Clock input P

DDR3A_CK_P

U44.D24 —

U36.K9, U37.K9 Clock enable

DDR3A_CKE

U44.M16 —

U36.L2, U37.L2 Chip select

DDR3A_CSN

U44.G14 —

U37.E3 Data bus

DDR3A_DQ0

U44.D14 —

U37.F7 Data bus

DDR3A_DQ1

U44.C12 —

U37.F2 Data bus

DDR3A_DQ2

U44.C14 —

U37.F8 Data bus

DDR3A_DQ3

U44.C10 —

U37.H3 Data bus

DDR3A_DQ4

U44.C13 —

U37.H8 Data bus

DDR3A_DQ5

U44.B10 —

U37.G2 Data bus

DDR3A_DQ6

U44.B14 —

U37.H7 Data bus

DDR3A_DQ7

U44.B11 —

1 2 ... 52 53 54 55 56 57 58 59 60 61 62 ... 79 80

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