Altera PHY IP Core Uživatelská příručka stáhnout pdf (Strana 101)

Name Direction Clock Domain Description

rx_coreclkin Input Clock

RX parallel clock that drives the read side clock of

the RX FIFO.

Table 2-62: TX and RX FIFO

Name Direction Clock Domain Description

tx_std_pcfifo_

full[<n>-1:0]

Output Synchronous

to the clock

driving the

write side of

the FIFO (tx_

coreclkin or

tx_clkout)

Indicates when the standard TX FIFO is full.

tx_std_pcfifo_

empty[<n>-1:0]

Output Synchronous

to the clock

driving the

write side of

the FIFO (tx_

coreclkin or

tx_clkout)

Indicates when the standard TX FIFO is empty.

rx_std_pcfifo_

full[<n>-1:0]

Output Synchronous

to the clock

driving the

read side of

the FIFO (rx_

coreclkin or

rx_clkout)

Indicates when the standard RX FIFO is full.

rx_std_pcfifo_

empty[<n>-1:0]

Output Synchronous

to the clock

driving the

read side of

the FIFO (rx_

coreclkin or

rx_clkout)

Indicates when the standard RX FIFO is empty.

Table 2-63: Rate Match FIFO

Name Direction Clock Domain Description

rx_std_rmfifo_

full[<n>-1:0]

Output Asynchronous Rate match FIFO full flag. When asserted the rate

match FIFO is full. You must synchronize this

signal. This port is only used for GigE mode.

2-70

Standard PCS Ports

UG-01143

2015.05.11

Altera Corporation

Implementing Protocols in Arria 10 Transceivers

Send Feedback

1 2 ... 96 97 98 99 100 101 102 103 104 105 106 ... 625 626

Komentáře k této Příručce

Žádné komentáře