Altera UG-01080 Uživatelská příručka

101 Innovation DriveSan Jose, CA 95134www.altera.com UG-01080-1.11User GuideAltera Transceiver PHY IP CoreDocument last updated for Altera Complete De

1–4 Chapter 1: IntroductionReset ControllerAltera Transceiver PHY IP Core User Guide December 2010 Altera CorporationFigure 1–2. Stratix V Device Bond

8–6 Chapter 8: Low Latency PHY IP CoreInterfacesAltera Transceiver PHY IP Core User Guide December 2010 Altera CorporationFigure 8–3 shows the interfa

Chapter 8: Low Latency PHY IP Core 8–7InterfacesDecember 2010 Altera Corporation Altera Transceiver PHY IP Core User GuideAvalon-MM PHY Management Int

8–8 Chapter 8: Low Latency PHY IP CoreInterfacesAltera Transceiver PHY IP Core User Guide December 2010 Altera CorporationSerial Data InterfaceTable 8

December 2010 Altera Corporation Altera Transceiver PHY IP Core User Guide9. Transceiver ReconfigurationControllerYou can use the Altera Transceiver

9–2 Chapter 9: Transceiver Reconfiguration ControllerRegister DescriptionsAltera Transceiver PHY IP Core User Guide December 2010 Altera Corporation1

Chapter 9: Transceiver Reconfiguration Controller 9–3Steps to Achieve PMA Controls ReconfigurationDecember 2010 Altera Corporation Altera Transceiver

9–4 Chapter 9: Transceiver Reconfiguration ControllerSteps to Achieve PMA Controls ReconfigurationAltera Transceiver PHY IP Core User Guide December 2

December 2010 Altera Corporation Altera Transceiver PHY IP Core User Guide10. Migrating from Stratix IV to Stratix VPreviously, Altera provided the AL

10–2 Chapter 10: Migrating from Stratix IV to Stratix VXAUI PHYAltera Transceiver PHY IP Core User Guide December 2010 Altera CorporationPort Differen

Chapter 10: Migrating from Stratix IV to Stratix V 10–3XAUI PHYDecember 2010 Altera Corporation Altera Transceiver PHY IP Core User Guidecoreclkout1xg

Chapter 1: Introduction 1–5Reset ControllerDecember 2010 Altera Corporation Altera Transceiver PHY IP Core User GuideIn non-bonded mode, separate CGBs

10–4 Chapter 10: Migrating from Stratix IV to Stratix VPCI Express PHY (PIPE)Altera Transceiver PHY IP Core User Guide December 2010 Altera Corporatio

Chapter 10: Migrating from Stratix IV to Stratix V 10–5PCI Express PHY (PIPE)December 2010 Altera Corporation Altera Transceiver PHY IP Core User Guid

10–6 Chapter 10: Migrating from Stratix IV to Stratix VPCI Express PHY (PIPE)Altera Transceiver PHY IP Core User Guide December 2010 Altera Corporatio

Chapter 10: Migrating from Stratix IV to Stratix V 10–7PCI Express PHY (PIPE)December 2010 Altera Corporation Altera Transceiver PHY IP Core User Guid

10–8 Chapter 10: Migrating from Stratix IV to Stratix VCustom PHYAltera Transceiver PHY IP Core User Guide December 2010 Altera CorporationCustom PHYT

Chapter 10: Migrating from Stratix IV to Stratix V 10–9Custom PHYDecember 2010 Altera Corporation Altera Transceiver PHY IP Core User GuidePort Differ

10–10 Chapter 10: Migrating from Stratix IV to Stratix VCustom PHYAltera Transceiver PHY IP Core User Guide December 2010 Altera Corporation

December 2010 Altera Corporation Altera Transceiver PHY IP Core User GuideAdditional InformationThis chapter provides additional information about the

Info–2 Additional InformationRevision HistoryAltera Transceiver PHY IP Core User Guide December 2010 Altera CorporationInterlaken PHY TransceiverDecem

Additional Information Info–3How to Contact AlteraDecember 2010 Altera Corporation Altera Transceiver PHY IP Core User GuideHow to Contact AlteraTo lo

1–6 Chapter 1: IntroductionReset ControllerAltera Transceiver PHY IP Core User Guide December 2010 Altera CorporationThe reset controller also include

Info–4 Additional InformationTypographic ConventionsAltera Transceiver PHY IP Core User Guide December 2010 Altera CorporationCourier typeIndicates si

Chapter 1: Introduction 1–7Reset ControllerDecember 2010 Altera Corporation Altera Transceiver PHY IP Core User Guide3. Finally, rx_ready is asserted

1–8 Chapter 1: IntroductionAvalon-MM PHY ManagementAltera Transceiver PHY IP Core User Guide December 2010 Altera CorporationAvalon-MM PHY ManagementY

December 2010 Altera Corporation Altera Transceiver PHY IP Core User Guide2. Getting StartedThis chapter provides a general overview of the Altera IP

2–2 Chapter 2: Getting StartedMegaWizard Plug-In Manager FlowAltera Transceiver PHY IP Core User Guide December 2010 Altera Corporation MegaWizard Pl

Chapter 2: Getting Started 2–3MegaWizard Plug-In Manager FlowDecember 2010 Altera Corporation Altera Transceiver PHY IP Core User Guide3. To select a

2–4 Chapter 2: Getting StartedMegaWizard Plug-In Manager FlowAltera Transceiver PHY IP Core User Guide December 2010 Altera Corporation8. Click Yes if

December 2010 Altera Corporation Altera Transceiver PHY IP Core User Guide3. 10GBASE-R PHY IP CoreThe Altera 10GBASE-R PHY IP core implements the func

Altera Transceiver PHY IP Core User Guide December 2010 Altera CorporationCopyright © 2010 Altera Corporation. All rights reserved. Altera, The Progra

3–2 Chapter 3: 10GBASE-R PHY IP CoreAltera Transceiver PHY IP Core User Guide December 2010 Altera CorporationTo make most effective use of this soft

Chapter 3: 10GBASE-R PHY IP Core 3–3Release InformationDecember 2010 Altera Corporation Altera Transceiver PHY IP Core User GuideRelease InformationTa

3–4 Chapter 3: 10GBASE-R PHY IP CorePerformance and Resource UtilizationAltera Transceiver PHY IP Core User Guide December 2010 Altera CorporationPerf

Chapter 3: 10GBASE-R PHY IP Core 3–5InterfacesDecember 2010 Altera Corporation Altera Transceiver PHY IP Core User GuideInterfacesFigure 3–3 illustrat

3–6 Chapter 3: 10GBASE-R PHY IP CoreInterfacesAltera Transceiver PHY IP Core User Guide December 2010 Altera CorporationSDR XGMII TX InterfaceTable 3–

Chapter 3: 10GBASE-R PHY IP Core 3–7InterfacesDecember 2010 Altera Corporation Altera Transceiver PHY IP Core User GuideSDR XGMII RX InterfaceTable 3–

3–8 Chapter 3: 10GBASE-R PHY IP CoreInterfacesAltera Transceiver PHY IP Core User Guide December 2010 Altera CorporationAvalon-MM InterfaceThe Avalon-

Chapter 3: 10GBASE-R PHY IP Core 3–9InterfacesDecember 2010 Altera Corporation Altera Transceiver PHY IP Core User GuideRegister DescriptionsTable 3–1

3–10 Chapter 3: 10GBASE-R PHY IP CoreInterfacesAltera Transceiver PHY IP Core User Guide December 2010 Altera CorporationPMA Channel Control and Statu

Chapter 3: 10GBASE-R PHY IP Core 3–11InterfacesDecember 2010 Altera Corporation Altera Transceiver PHY IP Core User GuideStatus InterfaceTable 3–11 de

December 2010 Altera Corporation Altera Transceiver PHY IP Core User GuideContentsChapter 1. IntroductionPCS . . . . . . . . . . . . . . . . . . . . .

3–12 Chapter 3: 10GBASE-R PHY IP CoreInterfacesAltera Transceiver PHY IP Core User Guide December 2010 Altera CorporationWhen connected to the hard PM

Chapter 3: 10GBASE-R PHY IP Core 3–13InterfacesDecember 2010 Altera Corporation Altera Transceiver PHY IP Core User GuideFigure 3–5 illustrates the cl

3–14 Chapter 3: 10GBASE-R PHY IP CoreTimeQuest Timing ConstraintsAltera Transceiver PHY IP Core User Guide December 2010 Altera CorporationSerial Inte

Chapter 3: 10GBASE-R PHY IP Core 3–15TimeQuest Timing ConstraintsDecember 2010 Altera Corporation Altera Transceiver PHY IP Core User GuideExample 3–1

3–16 Chapter 3: 10GBASE-R PHY IP CoreTimeQuest Timing ConstraintsAltera Transceiver PHY IP Core User Guide December 2010 Altera Corporation1 This .sdc

December 2010 Altera Corporation Altera Transceiver PHY IP Core User Guide4. XAUI PHY IP CoreThe Altera XAUI PHY IP core implements the IEEE 802.3 Cla

4–2 Chapter 4: XAUI PHY IP CoreDevice Family SupportAltera Transceiver PHY IP Core User Guide December 2010 Altera CorporationDevice Family SupportIP

Chapter 4: XAUI PHY IP Core 4–3Parameter SettingsDecember 2010 Altera Corporation Altera Transceiver PHY IP Core User GuideParameter SettingsTo config

4–4 Chapter 4: XAUI PHY IP CoreConfigurationsAltera Transceiver PHY IP Core User Guide December 2010 Altera CorporationFor a description of the PMA an

Chapter 4: XAUI PHY IP Core 4–5InterfacesDecember 2010 Altera Corporation Altera Transceiver PHY IP Core User GuideInterfacesFigure 4–3 illustrates th

iv ContentsAltera Transceiver PHY IP Core User Guide December 2010 Altera CorporationChapter 5. Interlaken PHY IP CoreDevice Family Support . . . . .

4–6 Chapter 4: XAUI PHY IP CoreInterfacesAltera Transceiver PHY IP Core User Guide December 2010 Altera CorporationFigure 4–4 illustrates the top-leve

Chapter 4: XAUI PHY IP Core 4–7InterfacesDecember 2010 Altera Corporation Altera Transceiver PHY IP Core User GuideThis interface runs at 156.25 MHz i

4–8 Chapter 4: XAUI PHY IP CoreInterfacesAltera Transceiver PHY IP Core User Guide December 2010 Altera CorporationAvalon-MM InterfaceThe Avalon-MM PH

Chapter 4: XAUI PHY IP Core 4–9InterfacesDecember 2010 Altera Corporation Altera Transceiver PHY IP Core User Guide0x042 [1:0]Wreset_control (write)Wr

4–10 Chapter 4: XAUI PHY IP CoreInterfacesAltera Transceiver PHY IP Core User Guide December 2010 Altera CorporationXAUI PCS0x081[31:2] — Reserved —[1

Chapter 4: XAUI PHY IP Core 4–11InterfacesDecember 2010 Altera Corporation Altera Transceiver PHY IP Core User Guide0x086[31:8] — Reserved —[7:4]R, st

4–12 Chapter 4: XAUI PHY IP CoreInterfacesAltera Transceiver PHY IP Core User Guide December 2010 Altera CorporationTransceiver Serial Data InterfaceT

Chapter 4: XAUI PHY IP Core 4–13InterfacesDecember 2010 Altera Corporation Altera Transceiver PHY IP Core User GuideClocks, Reset, and PowerdownFigure

4–14 Chapter 4: XAUI PHY IP CoreInterfacesAltera Transceiver PHY IP Core User Guide December 2010 Altera CorporationPMA Channel ControllerTable 4–13 d

Chapter 4: XAUI PHY IP Core 4–15InterfacesDecember 2010 Altera Corporation Altera Transceiver PHY IP Core User GuidePMA Control and Status Interface S

Contents vDecember 2010 Altera Corporation Altera Transceiver PHY IP Core User GuideAvalon-ST TX and RX Data Interface to the MAC . . . . . . . . .

4–16 Chapter 4: XAUI PHY IP CoreTimeQuest Timing ConstraintsAltera Transceiver PHY IP Core User Guide December 2010 Altera CorporationTimeQuest Timing

Chapter 4: XAUI PHY IP Core 4–17TimeQuest Timing ConstraintsDecember 2010 Altera Corporation Altera Transceiver PHY IP Core User Guide1 This .sdc file

4–18 Chapter 4: XAUI PHY IP CoreTimeQuest Timing ConstraintsAltera Transceiver PHY IP Core User Guide December 2010 Altera Corporation

December 2010 Altera Corporation Altera Transceiver PHY IP Core User Guide5. Interlaken PHY IP CoreInterlaken is a high speed serial communication pro

5–2 Chapter 5: Interlaken PHY IP CoreDevice Family SupportAltera Transceiver PHY IP Core User Guide December 2010 Altera Corporationf For more detaile

Chapter 5: Interlaken PHY IP Core 5–3InterfaceDecember 2010 Altera Corporation Altera Transceiver PHY IP Core User GuideInterfaceFigure 5–2 illustrate

5–4 Chapter 5: Interlaken PHY IP CoreInterfaceAltera Transceiver PHY IP Core User Guide December 2010 Altera Corporationf For more information about _

Chapter 5: Interlaken PHY IP Core 5–5InterfaceDecember 2010 Altera Corporation Altera Transceiver PHY IP Core User GuideAvalon-ST RX InterfaceTable 5–

5–6 Chapter 5: Interlaken PHY IP CoreInterfaceAltera Transceiver PHY IP Core User Guide December 2010 Altera CorporationAvalon Memory-Mapped (Avalon-M

Chapter 5: Interlaken PHY IP Core 5–7InterfaceDecember 2010 Altera Corporation Altera Transceiver PHY IP Core User Guide0x044[31:4,0] RWreset_fine_con

vi ContentsAltera Transceiver PHY IP Core User Guide December 2010 Altera Corporation

5–8 Chapter 5: Interlaken PHY IP CoreInterfaceAltera Transceiver PHY IP Core User Guide December 2010 Altera CorporationPLL InterfaceTable 5–9 describ

Chapter 5: Interlaken PHY IP Core 5–9Simulation TestbenchDecember 2010 Altera Corporation Altera Transceiver PHY IP Core User GuideOptional Clocks for

5–10 Chapter 5: Interlaken PHY IP CoreSimulation TestbenchAltera Transceiver PHY IP Core User Guide December 2010 Altera CorporationBoth the Verilog a

Chapter 5: Interlaken PHY IP Core 5–11Simulation TestbenchDecember 2010 Altera Corporation Altera Transceiver PHY IP Core User GuideExample 5–1. Testb

5–12 Chapter 5: Interlaken PHY IP CoreSimulation TestbenchAltera Transceiver PHY IP Core User Guide December 2010 Altera Corporation

December 2010 Altera Corporation Altera Transceiver PHY IP Core User Guide6. PCI Express PHY (PIPE) IP CoreThe Altera PCI Express PHY (PIPE) IP core i

6–2 Chapter 6: PCI Express PHY (PIPE) IP CoreResource UtilizationAltera Transceiver PHY IP Core User Guide December 2010 Altera CorporationResource Ut

Chapter 6: PCI Express PHY (PIPE) IP Core 6–3InterfacesDecember 2010 Altera Corporation Altera Transceiver PHY IP Core User GuideInterfacesFigure 6–2

6–4 Chapter 6: PCI Express PHY (PIPE) IP CoreInterfacesAltera Transceiver PHY IP Core User Guide December 2010 Altera CorporationAvalon-ST TX Input Da

Chapter 6: PCI Express PHY (PIPE) IP Core 6–5InterfacesDecember 2010 Altera Corporation Altera Transceiver PHY IP Core User GuideFigure 6–3 illustrate

December 2010 Altera Corporation Altera Transceiver PHY IP Core User Guide1. IntroductionThe Altera® Transceiver PHY IP Core User Guide describes the

6–6 Chapter 6: PCI Express PHY (PIPE) IP CoreInterfacesAltera Transceiver PHY IP Core User Guide December 2010 Altera CorporationPHY Management Signal

Chapter 6: PCI Express PHY (PIPE) IP Core 6–7InterfacesDecember 2010 Altera Corporation Altera Transceiver PHY IP Core User Guide0x044[31:4,0] RWreset

6–8 Chapter 6: PCI Express PHY (PIPE) IP CoreInterfacesAltera Transceiver PHY IP Core User Guide December 2010 Altera Corporation0x081[31:6] R Reserve

Chapter 6: PCI Express PHY (PIPE) IP Core 6–9InterfacesDecember 2010 Altera Corporation Altera Transceiver PHY IP Core User GuidePIPE InterfaceTable 6

6–10 Chapter 6: PCI Express PHY (PIPE) IP CoreInterfacesAltera Transceiver PHY IP Core User Guide December 2010 Altera Corporationpipe_txcomplianceSin

Chapter 6: PCI Express PHY (PIPE) IP Core 6–11InterfacesDecember 2010 Altera Corporation Altera Transceiver PHY IP Core User GuideFigure 6–4 illustrat

6–12 Chapter 6: PCI Express PHY (PIPE) IP CoreSimulationAltera Transceiver PHY IP Core User Guide December 2010 Altera CorporationSimulation When you

Chapter 6: PCI Express PHY (PIPE) IP Core 6–13SimulationDecember 2010 Altera Corporation Altera Transceiver PHY IP Core User GuideExample 6–1 shows th

6–14 Chapter 6: PCI Express PHY (PIPE) IP CoreSimulationAltera Transceiver PHY IP Core User Guide December 2010 Altera Corporation

December 2010 Altera Corporation Altera Transceiver PHY IP Core User Guide7. Custom PHY IP CoreThe Altera Custom PHY IP core is a generic PHY that you

1–2 Chapter 1: IntroductionAltera Transceiver PHY IP Core User Guide December 2010 Altera CorporationFigure 1–1 illustrates the top level modules that

7–2 Chapter 7: Custom PHY IP CorePerformance and Resource UtilizationAltera Transceiver PHY IP Core User Guide December 2010 Altera Corporation Preli

Chapter 7: Custom PHY IP Core 7–3Parameter SettingsDecember 2010 Altera Corporation Altera Transceiver PHY IP Core User GuideFigure 7–2 shows the top-

7–4 Chapter 7: Custom PHY IP CoreParameter SettingsAltera Transceiver PHY IP Core User Guide December 2010 Altera CorporationFigure 7–3 shows the top-

Chapter 7: Custom PHY IP Core 7–5Parameter SettingsDecember 2010 Altera Corporation Altera Transceiver PHY IP Core User GuideWord AlignmentThe word al

7–6 Chapter 7: Custom PHY IP CoreParameter SettingsAltera Transceiver PHY IP Core User Guide December 2010 Altera CorporationTable 7–5 provides more i

Chapter 7: Custom PHY IP Core 7–7Parameter SettingsDecember 2010 Altera Corporation Altera Transceiver PHY IP Core User GuideIf you enable the rate ma

7–8 Chapter 7: Custom PHY IP CoreInterfacesAltera Transceiver PHY IP Core User Guide December 2010 Altera CorporationTable 7–8 lists the Datapath opti

Chapter 7: Custom PHY IP Core 7–9InterfacesDecember 2010 Altera Corporation Altera Transceiver PHY IP Core User Guide1 The block diagram shown in the

7–10 Chapter 7: Custom PHY IP CoreInterfacesAltera Transceiver PHY IP Core User Guide December 2010 Altera CorporationAvalon-MM PHY Management Interfa

Chapter 7: Custom PHY IP Core 7–11InterfacesDecember 2010 Altera Corporation Altera Transceiver PHY IP Core User GuidePHY Management SignalsTable 7–11

Chapter 1: Introduction 1–3PCSDecember 2010 Altera Corporation Altera Transceiver PHY IP Core User GuideThe following sections provide a brief introdu

7–12 Chapter 7: Custom PHY IP CoreInterfacesAltera Transceiver PHY IP Core User Guide December 2010 Altera Corporation0x044[31:4,0] RWreset_fine_contr

Chapter 7: Custom PHY IP Core 7–13InterfacesDecember 2010 Altera Corporation Altera Transceiver PHY IP Core User GuideClock InterfaceTable 7–13 descri

7–14 Chapter 7: Custom PHY IP CoreInterfacesAltera Transceiver PHY IP Core User Guide December 2010 Altera CorporationTransceiver Serial Data Interfac

Chapter 7: Custom PHY IP Core 7–15InterfacesDecember 2010 Altera Corporation Altera Transceiver PHY IP Core User GuideDynamic Partial Reconfiguration

7–16 Chapter 7: Custom PHY IP CoreInterfacesAltera Transceiver PHY IP Core User Guide December 2010 Altera Corporation

December 2010 Altera Corporation Altera Transceiver PHY IP Core User Guide8. Low Latency PHY IP CoreThe Altera Low Latency IP core receives and transm

8–2 Chapter 8: Low Latency PHY IP CoreDevice Family SupportAltera Transceiver PHY IP Core User Guide December 2010 Altera CorporationDevice Family Sup

Chapter 8: Low Latency PHY IP Core 8–3Parameter SettingsDecember 2010 Altera Corporation Altera Transceiver PHY IP Core User GuideThe parameters on th

8–4 Chapter 8: Low Latency PHY IP CoreParameter SettingsAltera Transceiver PHY IP Core User Guide December 2010 Altera CorporationTable 8–4 describes

Chapter 8: Low Latency PHY IP Core 8–5InterfacesDecember 2010 Altera Corporation Altera Transceiver PHY IP Core User GuideInterfacesFigure 8–2 illustr