Altera Stratix V Avalon-ST Uživatelský manuál Strana 105
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- Tabulka s obsahem
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Hodnocené. / 5. Na základě hodnocení zákazníků
Bits Register Description Default Value Access
[3:0] Reserved. 0 RO
[4] Indicates the presence of PCI Extended Capabilities. This bit is
hardwired to 1.
0 RW1C
[7:5] Reserved. 0 RO
[8] Master Data Parity Error. Enabled when the PF PCI Command
Register Parity Error Response bit is set. When set, indicates one
of the following conditions:
• The device has received a Poisoned Completion from the link
for this VF
• This VF has transmitted a Poisoned Memory Write request on
the link
RW1C
[10:9] Reserved. 0 RO
[11] Signal Target Abort. When set, this VF has sent a Completion to
the link with Completer Abort (CA) stats.
0 RW1C
[12] Received Target Abort. When set, indicates that this VF has
received a Completion from the link with the CA status.
0 RW1C
[13] Received Master Abort. When set, indicates that this VF has
received a Completion from the link with the Unsupported
Request (UR) status.
0 RW1C
[14] Signaled System Error. When set, indicates that this VF has
transmitted a Fatal or Non-Fatal error message on the link to the
Root Complex. Enabled when the PF PCI Command Register
SERR Enable bit is set.
0 RW1C
[15] Received Master Abort. When set, indicates the VF has received a
Completion from the link with the Unsupported Request (UR)
status.
0 RW1C
Table 5-48: PCI Express Capability List Register for VFs
Bits Register Description Default Value Access
[31:19] Hardwired to 0. 0 RO
[18:16] Version ID: Version of PCI Express Capability. 2 RW
[15:8] Next Capability Pointer: Points to NULL. 0 RO
[7:0] Capability ID assigned by PCI-SIG. 0x10 RO
Table 5-49: PCI Express Device Control and Status Registers for VFs
Bits Register Description Default Value Access
Control Register
[14:0] Reserved. 0 RO
UG-01097_sriov
2014.12.15
Virtual Function Registers
5-31
Registers
Altera Corporation
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- User Guide 1
- Datasheet 2
- Features 3
- Interface 4
- Release Information 7
- Device Family Support 7
- Example Designs 8
- Debug Features 8
- IP Core Verification 9
- Recommended Speed Grades 10
- Related Information 11
- Subscribe 12
- Qsys Subsystem Description 13
- Parameter Value 15
- Directory Description 16
- Parameter Settings 21
- Parameter Value Description 22
- SR-IOV System Settings 24
- Interrupt Capabilities 27
- Device Capabilities 29
- Error Reporting 30
- Link Capabilities 31
- Slot Capabilities 32
- Power Management 33
- PHY Characteristics 34
- Simulation Options 35
- Avalon-ST TX Interface 37
- Signal Direction Description 38
- Avalon‑ST RX Interface 40
- BAR Hit Signals 43
- Completion Side Band Signals 45
- Signal Directi 46
- Description 46
- Clock Signals 48
- Interrupt Interface 49
- Implementing MSI-X Interrupts 55
- LMI Signals 57
- Serial Data Signals 65
- Test Signals 70
- PIPE Interface Signals 71
- Byte Address 77
- MSI Registers 80
- MSI-X Capability Structure 82
- VF Device ID Register 96
- Page Size Registers 96
- Lane Error Status Register 98
- Bits Register Description 99
- Default Value 99
- Altera Corporation 100
- Registers 100
- Send Feedback 100
- Virtual Function Registers 102
- Name Description 103
- Reset and Clocks 107
- Hard IP for PCI Express 108
- Example Design 108
- UG-01097_sriov 109
- 2014.12.15 109
- Function Level Reset (FLR) 111
- Clock Domains 111
- Clock Summary 114
- Interrupts 115
- Error Handling 118
- Physical Layer Errors 119
- Data Link Layer Errors 119
- Transaction Layer Errors 120
- Error Type Description 121
- Status Bit Conditions 123
- IP Core Architecture 125
- Top-Level Interfaces 126
- Clocks and Reset 126
- Transceiver Reconfiguration 126
- Data Link Layer 127
- Physical Layer 129
- TX Packets 130
- Design Implementation 136
- CONF_DONE 137
- Endpoint Reset 137
- Root Port Reset 137
- SDC Timing Constraints 138
- Debugging 143
- Setting Up Simulation 146
- Use Third-Party PCIe Analyzer 148
- BIOS Enumeration Issues 148
- Address[31:2] 149
- Figure A-6: I/O Read Request 151
- Additional Information 155
- Typographic Conventions 156
- Visual Cue Meaning 157
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