Altera RapidIO II MegaCore Function Uživatelský manuál stáhnout pdf (Strana 28)

2–10 Chapter 2: Getting Started

Instantiating Multiple RapidIO II IP Cores

RapidIO II MegaCore Function August 2014 Altera Corporation

User Guide

Instantiating Multiple RapidIO II IP Cores

If you want to instantiate multiple RapidIO II IP cores that target an Arria V, Arria V

GZ, Cyclone V, or Stratix V device, a few additional steps are required. These steps are

not relevant for variations that target an Arria 10 device.

The Arria V, Arria V GZ, Cyclone V, and Stratix V transceivers are configured with the

Altera Native PHY IP core. When your design contains multiple RapidIO II IP cores,

the Quartus II Fitter handles the merge of multiple Native PHY IP cores in the same

transceiver block automatically, if they meet the merging requirements specified in

the Altera Transceiver PHY IP Core User Guide.

If you have different RapidIO II IP cores in different transceiver blocks on your

device, you may choose to include multiple Transceiver Reconfiguration Controllers

in your design. However, you must ensure that the Transceiver Reconfiguration

Controllers that you add to your design have the correct number of interfaces to

control dynamic reconfiguration of all your RapidIO II IP core transceivers. The

correct total number of reconfiguration interfaces is the sum of the reconfiguration

interfaces for each RapidIO II IP core; the number of reconfiguration interfaces for

each RapidIO II IP core is the number of channels plus one. You must ensure that the

reconfig_togxb

and

reconfig_fromgxb

signals of an individual RapidIO II IP core

connect to a single Transceiver Reconfiguration Controller.

For example, if your design includes one ×4 RapidIO II IP core and three ×1

RapidIO II IP cores, the Transceiver Reconfiguration Controllers in your design must

include eleven dynamic reconfiguration interfaces: five for the ×4 RapidIO II IP core,

and two for each of the ×1 RapidIO II IP cores. The dynamic reconfiguration interfaces

connected to a single RapidIO II IP core must belong to the same Transceiver

Reconfiguration Controller. In most cases, your design has only a single Transceiver

Reconfiguration Controller, which has eleven dynamic reconfiguration interfaces. If

you choose to use two Transceiver Reconfiguration Controllers, for example, to

accommodate placement and timing constraints for your design, each of the

RapidIO II IP cores must connect to a single Transceiver Reconfiguration Controller.

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