Altera QDRII SRAM Controller MegaCore Function Uživatelský manuál stáhnout pdf (Strana 46)

3–14 MegaCore Version 9.1 Altera Corporation

QDRII SRAM Controller MegaCore Function User Guide November 2009

Interfaces & Signals

Figure 3–10. Write—Burst of Four (Narrow Mode)

This section does not illustrate the burst of two example, because you can

transfer any data at any address in every Avalon clock cycle. The timing

of the qdrii_a signal is different, refer to Figure 3–7 on page 3–11.

Bursts with Pauses

There are no pauses when using a burst of two memories. For the burst of

four, there are some pauses (depending on the mode). In narrow mode, if

the transfers are to consecutive addresses all the time, no pause occurs. If

the transfers are to non-consecutive addresses, a pause may occur, refer

to Figure 3–11 on page 3–15. a pause occurs only in the following

conditions:

■ A one-cycle write to address <a> followed straight away by a two-

cycle transfer to addresses <b> and <b + 1>

■ The second half of the transfer to <b> is paused for a clock cycle

avl_write

avl_data_wr[35:0]

avl_adr_wr[19:0]

avl_wait_request_wr

system_clk

qdrii_d[17:0]

qdrii_a[19:0]

qdrii_bwsn[1:0]

qdrii_wpsn

00010002 0003000400030004

0002 0003

0001 0002 0003 00040004

0002

0000

avl_clk

avl_clock_wr

1 2 ... 41 42 43 44 45 46 47 48 49 50 51 ... 67 68

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Altera QDRII SRAM Controller MegaCore Function Uživatelský manuál Strana 46