Altera QDRII SRAM Controller MegaCore Function Uživatelský manuál stáhnout pdf (Strana 26)

2–16 MegaCore Version 9.1 Altera Corporation

QDRII SRAM Controller MegaCore Function User Guide November 2009

Simulate the Example Design

4. Set the Tcl variable gRTL_DELAYS to 1, which tells the testbench to

model the extra delays in the system necessary for RTL simulation.

5. Configure your simulator to use transport delays, a timestep of

picoseconds and to include the auk_qdrii_lib, sgate_ver, lpm_ver,

altera_mf_ver, and <device name>_ver libraries.

Verilog HDL Gate-Level Simulations

For Verilog HDL simulations with gate-level models, follow these steps:

auk_qdrii_lib <project directory>/<variation name>_auk_qdrii_sram_clk_gen.v

<project directory>/<variation name>_auk_qdrii_sram_addr_cmd_reg.v

<project directory>/<variation name>_auk_qdrii_sram_cq_cqn_group.v

<project directory>/<variation name>_auk_qdrii_sram_read_group.v

<project directory>/<variation

name>_auk_qdrii_sram_capture_group_wrapper.v

<project directory>/<variation name>_auk_qdrii_sram_resynch_reg.v

<project directory>/<variation name>_auk_qdrii_sram_write_group.v

<project directory>/<variation name>_auk_qdrii_sram_datapath.v

<project directory>/<variation name>_auk_qdrii_sram_test_group.v

<project directory>/<variation name>_auk_qdrii_sram_train_wrapper.v

<project directory>/<variation name>_auk_qdrii_sram_pipeline_wdata.v

<project directory>/<variation name>_auk_qdrii_sram_pipeline_rdata.v

<project directory>/<variation

name>_auk_qdrii_sram_pipeline_addr_cmd.v

<project directory>/<variation

name>_auk_qdrii_sram_pipe_resynch_wrapper.v

<project directory>/<variation

name>_auk_qdrii_sram_avalon_controller_ipfs_wrap.vo

<project directory>/<variation name>_auk_qdrii_sram.v

<project directory>/<variation name>.v

<project directory>/qdrii_pll_stratixii.v

<project directory>/<variation name>_auk_qdrii_sram_dll.v

<project directory>/<variation name>_auk_qdrii_sram_example_driver.v

<project directory>/<project name>.v

<project directory>/testbench/<project name>_tb.vhd

Table 2–4. Files to Compile—Verilog HDL IP Functional Simulation Models (Part 2 of 2)

Library Filename

1 2 ... 21 22 23 24 25 26 27 28 29 30 31 ... 67 68

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Altera QDRII SRAM Controller MegaCore Function Uživatelský manuál Strana 26