Altera PCI Compiler Uživatelský manuál stáhnout pdf (Strana 335)

Altera Corporation User Guide Version 11.1 8–5

October 2011 PCI Compiler

Testbench

Table 8–3 shows the testbench's target termination support. The master

transactor and the local master respond to the target terminations by

terminating the transaction gracefully and releasing the PCI bus.

Master Transactor (mstr_tranx)

The master transactor simulates the master behavior on the PCI bus. It

serves as an initiator of PCI transactions for Altera PCI testbench. The

master transactor has three main sections:

■ PROCEDURES (VHDL) or TASKS (Verilog HDL)

■ INITIALIZATION

■ USER COMMANDS

PROCEDURES and TASKS Sections

The PROCEDURES (VHDL) and TASKS (Verilog HDL) sections define

the events that are executed for the user commands supported by the

master transactor. The events written in the PROCEDURES and TASKS

sections follow the phases of a standard PCI transaction as defined by the

PCI Local Bus Specification, Revision 3.0, including:

■ Address phase

■ Turn-around phase (read transactions)

■ Data phases

■ Turn-around phase

Configuration write

Memory read multiple

Dual address cycle

Memory read line

Memory write and invalidate

Table 8–2. PCI Testbench PCI Bus Transaction Support (Part 2 of 2)

Transactions Master Transactor Target Transactor Local Master Local Target

Table 8–3. PCI Testbench Target Termination Support

Features Master Transactor Target Transactor

Target abort

Target retry

Target disconnect

1 2 ... 330 331 332 333 334 335 336 337 338 339 340 ... 359 360

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Altera PCI Compiler Uživatelský manuál Strana 335