Altera IP Compiler for PCI Express Uživatelský manuál stáhnout pdf (Strana 277)

Chapter 15: Testbench and Design Example 15–45

BFM Procedures and Functions

August 2014 Altera Corporation IP Compiler for PCI Express User Guide

■ When

ebfm_log_set_stop_on_msg_mask

is called, the simulation can be stopped

after the message is displayed, based on the value of the bit mask.

ebfm_log_stop_sim VHDL Procedure or Verilog HDL Function

The

ebfm_log_stop_sim

procedure stops the simulation.

ebfm_log_set_suppressed_msg_mask Procedure

The

ebfm_log_set_suppressed_msg_mask

procedure controls which message types

are suppressed.

Table 15–40. ebfm_display Procedure

Location altpcietb_bfm_log.v or altpcietb_bfm_log.vhd

Syntax

VHDL: ebfm_display(msg_type, message)

Verilog HDL: dummy_return:=ebfm_display(msg_type, message);

Argument

msg_type

Message type for the message. Should be one of the constants defined in Table 15–39 on

page 15–44.

message

In VHDL, this argument is VHDL type

string

and contains the message text to be displayed.

In Verilog HDL, the message string is limited to a maximum of 100 characters. Also, because

Verilog HDL does not allow variable length strings, this routine strips off leading characters of

8’h00 before displaying the message.

Return

always 0

Applies only to the Verilog HDL routine.

Table 15–41. ebfm_log_stop_sim Procedure

Location altpcietb_bfm_log.v or altpcietb_bfm_log.vhd

Syntax

VHDL:

ebfm_log_stop_sim(success

)

Verilog VHDL:

return:=ebfm_log_stop_sim(success

);

Argument

success

When set to a 1, this process stops the simulation with a message indicating successful

completion. The message is prefixed with

SUCCESS

Otherwise, this process stops the simulation with a message indicating unsuccessful

completion. The message is prefixed with

FAILURE

Return Always 0 This value applies only to the Verilog HDL function.

Table 15–42. ebfm_log_set_suppressed_msg_mask Procedure

Location altpcietb_bfm_log.v or altpcietb_bfm_log.vhd

Syntax

bfm_log_set_suppressed_msg_mask (msg_mask)

Argument

msg_mask

In VHDL, this argument is a subtype of

std_logic_vector

EBFM_MSG_MASK.

This vector

has a range from

EBFM_MSG_ERROR_CONTINUE

downto

EBFM_MSG_DEBUG

In Verilog HDL, this argument is

reg [EBFM_MSG_ERROR_CONTINUE: EBFM_MSG_DEBUG].

In both languages, a 1 in a specific bit position of the

msg_mask

causes messages of the type

corresponding to the bit position to be suppressed.

1 2 ... 272 273 274 275 276 277 278 279 280 281 282 ... 371 372

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