Altera Interlaken MegaCore Function Uživatelský manuál Strana 64
- Strana / 90
- Tabulka s obsahem
- KNIHY
Hodnocené. / 5. Na základě hodnocení zákazníků
6–2 Chapter 6: Qsys Design Examples
Interlaken Sample Channel Client Component
Interlaken MegaCore Function June 2012 Altera Corporation
User Guide
f For more information about the interconnect fabric that Qsys generates, refer to the
Qsys Interconnect chapter in volume 1 of the Quartus II Handbook. For more
information about Qsys, refer to the Creating a System with Qsys chapter in volume 1 of
the Quartus II Handbook.
The design example files are provided in the Interlaken IP core installation directory.
You can use them as a basis for developing your own testbench for your Interlaken
MegaCore function variation. Based on the example, you can create your own stimuli
and verification criteria, using the Interlaken Sample Channel Client component
available in the Qsys tool.
Interlaken Sample Channel Client Component
The design examples implement each channel client with an Interlaken Sample
Channel Client component.
The Interlaken Sample Channel Client is a component in the Component Library
panel in the Qsys system integration tool. The only parameter available in its
parameter editor is Width of datapath in bits, which must match the datapath width
of the Interlaken MegaCore function to which it connects. However, its instantiation
relies on values being assigned to the additional parameters shown in Table 6–2.
The Interlaken Sample Channel Client sends data samples on the channel to which it
is connected in the RX application interface. Each data sample is some number of bits
that fits in
WORDS
number of 64-bit (8-byte) words. These are the valid bits in the
transmission. An internal register of size
LOG_WORDS
holds the number of 64-bit words
with at least one valid bit in them, and an internal register of size
EMPTY_BITS
holds
the number of bytes with no valid bits in them. The
LOG_WORDS
and
EMPTY_BITS
parameters can be derived from the value of
WORDS
, but are provided as separate
parameters for legibility.
Table 6–2. Interlaken Sample Channel Client Hidden Parameters
Parameter Description Default Value
WORDS
Number of 64-bit words in each data sample. (Not all bits need
be valid). Value is one of 2, 4, or 8, depending on the DUT
variation.
8
LOG_WORDS
Size of the internal register that holds the number of valid
words in the current transmission in or out. Value is 2, 3, or 4,
depending on the DUT variation, because holding a number
from 0 to
WORDS
requires log
2
(
WORDS
) + 1 bits.
4
EMPTY_BITS
Size of the internal register that holds the number of empty
bytes in transmissions in and out of the Interlaken Sample
Channel Client. Value is 4, 5, or 6, depending on the DUT
variation, because holding a number from 0 to 8, 0 to 16, or 0
to 64 requires 4, 5, or 6 bits.
6
BUFFER_WORDS
Number of 64-bit words in
TX_STRING
and
RX_STRING
vectors. Default value is
WORDS
× 2.
WORDS
× 2
TX_STRING
String from which outgoing data samples are derived. Length is
BUFFER_WORDS
× 64.
RX_STRING
String against which to check Interlaken RX incoming data
samples after they pass through the channel interface.
- User Guide 1
- Interlaken MegaCore Function 1
- Contents 3
- Chapter 5. Signals 4
- Contents v 5
- Features 7
- Device Family Support 8
- MegaCore Verification 9
- Release Information 10
- Installation and Licensing 10
- OpenCore Evaluation 12
- 2. Getting Started 13
- Qsys Design Flow Summary 14
- Qsys Design Flow 16
- Specifying Parameters 17
- Completing the Qsys System 18
- Simulating the System 18
- Specifying Constraints 19
- I/O Standard Constraints 20
- 3. Parameter Settings 23
- Lane Rate 24
- Number of Words in Meta Frame 24
- Exclude Transceiver 24
- Burst Parameters 25
- 4. Functional Description 27
- Architecture Overview 28
- Interfaces Overview 28
- Note to Table 4–1: 29
- Avalon-ST Interface 30
- Clocking and Reset Structure 31
- MAC Clock Verified Frequency 35
- PCS Clock Frequencies 36
- Transmit Path 37
- Receive Path 43
- Channel Filtering Blocks 45
- Packet Regrouper 45
- Calendar and Status Block 46
- Lane Status Block 47
- High-Speed I/O Block 48
- Transceivers 49
- 5. Signals 53
- Exclude transceivers 54
- Chapter 5: Signals 5–3 55
- Note to Table 5–2: 56
- Note to Table 5–3: 56
- Application Interface Signals 57
- Note to Table 5–6: 58
- Chapter 5: Signals 5–7 59
- Note to Table 5–8: 60
- Note to Table 5–9: 61
- Note to Table 5–10: 61
- Note to Table 5–11: 62
- Note to Table 5–12: 62
- Transceiver Banks 63
- Running a Design Example 65
- Setting Up the Design Example 66
- Function 69
- Simulation 73
- Reset Signals 79
- Required Reset Sequence 80
- Additional Information 87
- Typographic Conventions 88
- Visual Cue Meaning 89
- Info–4 Additional Information 90
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