Altera Integer Arithmetic IP Uživatelský manuál Strana 154
- Strana / 157
- Tabulka s obsahem
- KNIHY
Hodnocené. / 5. Na základě hodnocení zákazníků
Parameters
The following table lists the parameters for the PARALLEL_ADD megafunction.
Table 12-4: PARALLEL_ADD Megafunction Parameters
Parameter Name Type Required Description
WIDTH Integer Yes Specifies the width of the data[] input port.
SIZE Integer Yes Specifies the number of inputs to add.
WIDTHR Integer Yes Specifies the width of the result[] output
port.
SHIFT Integer Yes Specifies the relative shift of the data vectors.
NEW_SUBTRACT String No Specifies whether to add or subtract the most
significant input word bit. Values are NO or
YES. If omitted, the default value is NO.
REPRESENTATION String No Specifies whether the input is signed or
unsigned. Values are UNSIGNED or SIGNED. If
omitted, the default value is UNSIGNED.
PIPELINE Integer No Specifies the value, in clock cycles, of the
output latency.
RESULT_ALIGNMENT String No Specifies the alignment of the result port.
Values are MSB or LSB. If omitted, the default
value is LSB.
INTENDED_DEVICE_FAMILY String No This parameter is used for modeling and
behavioral simulation purposes. Create the
ALTCDR_RX megafunction with the
MegaWizard Plug-In Manager to calculate the
value for this parameter.
LPM_HINT String No
When you instantiate a library of parameter‐
ized modules (LPM) function in a VHDL
Design File (.vhd), you must use the LPM_
HINT parameter to specify an Altera-specific
parameter. For example: LPM_HINT =
"CHAIN_SIZE = 8, ONE_INPUT_IS_
CONSTANT = YES"
The default value is UNUSED.
LPM_TYPE String No Identifies the library of parameterized
modules (LPM) entity name in VHDL design
files.
Design Example: Shift Accumulator
12-4
Parameters
UG-01063
2014.12.19
Altera Corporation
PARALLEL_ADD (Parallel Adder)
Send Feedback
- 101 Innovation Drive 1
- San Jose, CA 95134 1
- Contents 2
- IP Cores Function Overview 6
- Design Example Files 7
- Using the Parameter Editor 9
- UG-01063 10
- 2014.12.19 10
- Legacy parameter 12
- Upgrading IP Cores 13
- Related Information 16
- Quartus II 17
- Design Flow 17
- Gate-Level Simulation 17
- RTL Simulation 17
- Simulating Altera Designs 18
- LPM_COUNTER (Counter) 19
- LPM_DIVIDE (Divider) 26
- LPM_MULT (Multiplier) 32
- LPM_MULT Ports 34
- LPM_MULT Parameters 35
- Decoder) 39
- ALTECC_ENCODER Features 40
- Ports (ALTECC_ENCODER) 45
- Ports (ALTECC_DECODER) 45
- Parameters (ALTECC_ENCODER) 46
- Parameters (ALTECC_DECODER) 46
- ALTERA_MULT_ADD 54
- ALTERA_MULT_ADD Parameters 65
- Coefficient Multiplier) 74
- ALTMULT_ACCUM 82
- ALTMULT_ACCUM Ports 85
- ALTMULT_ACCUM Parameters 87
- Altera Corporation 101
- Send Feedback 101
- ALTMULT_ADD (Multiply-Adder) 102
- ALTMULT_ADD 103
- Features 104
- Pre-adder 105
- Pre-adder Input Mode 106
- Pre-adder Square Mode 106
- Pre-adder Constant Mode 107
- Systolic Delay Register 108
- Pre-load Constant 111
- Double Accumulator 111
- Verilog HDL Prototype 112
- VHDL Component Declaration 112
- VHDL LIBRARY_USE Declaration 113
- ALTMULT_ADD Ports 113
- ALTMULT_ADD Parameters 115
- Parameter Name Type Requi 116
- Description 116
- Subscribe 138
- Complex Multiplication 139
- Canonical Representation 139
- Conventional Representation 140
- ALTMULT_COMPLEX Ports 143
- ALTMULT_COMPLEX Parameters 143
- ALTSQRT (Integer Square Root) 147
- Parameters 149
- PARALLEL_ADD (Parallel Adder) 151
- Document Revision History 156
- Date Version Changes 157
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