Altera Designing With Low-Level Primitives Uživatelský manuál stáhnout pdf (Strana 54)

2–32 Altera Corporation

Designing with Low-Level Primitives User Guide April 2007

Primitives

Example 2–26. LUT_INPUT Primitive Instantiation, Verilog HDL

lut_input <instance_name> (.in(<input_wire1), .out(<output_wire>)

Example 2–27 shows a VHDL component declaration for a LUT_INPUT

primitive instantiation.

Example 2–27. LUT_INPUT Primitive Instantiation, VHDL Component Declaration

COMPONENT LUT_INPUT

PORT (a_in : IN STD_LOGIC;

a_out: OUT STD_LOGIC);

END COMPONENT;

LUT_OUTPUT

The LUT_OUTPUT buffer specifies a LUT function. The LUT_OUTPUT

buffer works like an LCELL buffer with the additional detail of specifying

the inputs and without the requirement that the LUT function has

become a hard output. The LUT_INPUT buffer is the input for a

LUT_OUTPUT buffer. The logical functionality of the LUT_OUTPUT and

LUT_INPUT buffers is a simple wire, but together they identify LUT

boundaries.

Example 2–28 shows a Verilog HDL example of a LUT_OUTPUT primitive

instantiation.

Example 2–28. LUT_OUTPUT Primitive Instantiation, Verilog HDL

lut_output <instance_name> (.in(<input_wire>), .out(<output_wire>)

Example 2–29 shows a VHDL component declaration for a LUT_OUTPUT

primitive instantiation.

Example 2–29. LUT_OUTPUT Primitive Instantiation, VHDL Component Declaration

COMPONENT LUT_OUTPUT

PORT (a_in : IN STD_LOGIC;

a_out : OUT STD_LOGIC);

END COMPONENT;

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Altera Designing With Low-Level Primitives Uživatelský manuál Strana 54