Altera Cyclone V SoC Development Board Uživatelský manuál stáhnout pdf (Strana 50)

2–42 Chapter 2: Board Components

Memory

Cyclone V SoC Development Board November 2013 Altera Corporation

Reference Manual

DDR3_HPS_A14

H25 1.5-V SSTL Class I Address bus

DDR3_HPS_BA0

E29 1.5-V SSTL Class I Bank address bus

DDR3_HPS_BA1

J24 1.5-V SSTL Class I Bank address bus

DDR3_HPS_BA2

J23 1.5-V SSTL Class I Bank address bus

DDR3_HPS_CASN

E27 1.5-V SSTL Class I Row address select

DDR3_HPS_CKE

L29 1.5-V SSTL Class I Column address select

DDR3_HPS_CLK_P

L23

Differential 1.5-V

SSTL Class I

Differential output clock

DDR3_HPS_CLK_N

M23

Differential 1.5-V

SSTL Class I

Differential output clock

DDR3_HPS_CSN

H24 1.5-V SSTL Class I Chip select

DDR3_HPS_DM4

W27 1.5-V SSTL Class I Write mask byte lane

DDR3_HPS_DQ32

W26 1.5-V SSTL Class I Data bus

DDR3_HPS_DQ33

R24 1.5-V SSTL Class I Data bus

DDR3_HPS_DQ34

U27 1.5-V SSTL Class I Data bus

DDR3_HPS_DQ35

V28 1.5-V SSTL Class I Data bus

DDR3_HPS_DQ36

T25 1.5-V SSTL Class I Data bus

DDR3_HPS_DQ37

U25 1.5-V SSTL Class I Data bus

DDR3_HPS_DQ38

V27 1.5-V SSTL Class I Data bus

DDR3_HPS_DQ39

Y29 1.5-V SSTL Class I Data bus

DDR3_HPS_DQS_P4

T24

Differential 1.5-V

SSTL Class I

Data strobe P byte lane 4

DDR3_HPS_DQS_N4

T23

Differential 1.5-V

SSTL Class I

Data strobe N byte lane 4

DDR3_HPS_ODT

H28 1.5-V SSTL Class I On-die termination enable

DDR3_HPS_RASN

D30 1.5-V SSTL Class I Row address select

DDR3_HPS_RESETN

P30 1.5-V SSTL Class I Reset

DDR3_HPS_WEN

C28 1.5-V SSTL Class I Write enable

DDR3_HPS_ZQ01

— 1.5-V SSTL Class I ZQ impedance calibration

DDR3 x16 (U22)

DDR3_HPS_A0

F26 1.5-V SSTL Class I Address bus

DDR3_HPS_A1

G30 1.5-V SSTL Class I Address bus

DDR3_HPS_A2

F28 1.5-V SSTL Class I Address bus

DDR3_HPS_A3

F30 1.5-V SSTL Class I Address bus

DDR3_HPS_A4

J25 1.5-V SSTL Class I Address bus

DDR3_HPS_A5

J27 1.5-V SSTL Class I Address bus

DDR3_HPS_A6

F29 1.5-V SSTL Class I Address bus

DDR3_HPS_A7

E28 1.5-V SSTL Class I Address bus

DDR3_HPS_A8

H27 1.5-V SSTL Class I Address bus

Table 2–33. DDR3 SDRAM Pin Assignments, Schematic Signal Names, and Functions (Part 2 of 5)

Board

Reference

Schematic

Signal Name

Cyclone V SoC

Pin Number

I/O Standard Description

1 2 ... 45 46 47 48 49 50 51 52 53 54 55 ... 67 68

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