Altera Cyclone IV GX FPGA Development Board Uživatelský manuál stáhnout pdf (Strana 4)

iv Contents

Cyclone IV GX FPGA Development Board May 2013 Altera Corporation

Reference Manual

Additional Information

Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–1

How to Contact Altera . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–1

Typographic Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–1

1 2 3 4 5 6 7 8 9 ... 59 60

Reference Manual 1
Contents 3
Additional Information 4
1. Overview 5
1–2 Chapter 1: Overview 6
Board Component Blocks 6
EP4CGX150DF31 7
Handling the Board 8
2. Board Components 9
Board Overview 10
I/O Resources 14
Note to Table 2–4: 15
Configuration 20
Figure 2–4. JTAG Chain 21
Note to Table 2–7: 22
Status Elements 24
Board Settings DIP Switch 25
Note to Table 2–10: 25
Setup Elements 25
JTAG Chain Select DIP Switch 26
Notes to Table 2–12: 26
PCIe Control DIP Switch 27
Configuration Settings 27
Note to Table 2–14: 27
Notes to Table 2–16: 27
Clock Circuitry 28
User-Defined Push Buttons 29
User-Defined LEDs 30
General User-Defined LEDs 30
HSMC User-Defined LEDs 30
User-Defined DIP Switch 31
Note to Table 2–26: 32
General User Input/Output 33
Notes to Table 2–29: 35
10/100/1000 Ethernet 36
High-Speed Mezzanine Cards 37
DDR2 SDRAM 46
DDR2 SDRAM Top Port 47
DDR2 SDRAM Bottom Port 49
Power Supply 54
Power Distribution System 55
Power Measurement 56
Notes to Table 2–47: 57
Note to Table: 59
Typographic Conventions 60

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