Altera Cyclone IV GX FPGA Development Board Uživatelský manuál stáhnout pdf (Strana 17)

Chapter 2: Board Components 2–9

MAX II CPLD EPM2210 System Controller

May 2013 Altera Corporation Cyclone IV GX FPGA Development Board

Reference Manual

FACTORY_CONFIGn

1.8-V

G12 — Factory configuration enable

FLASH_ADVn

L13 F24 FSM bus flash memory address valid

FLASH_RESETn

M15 A28 FSM bus flash memory reset

FLASH_WEn

L12 C13 FSM bus flash memory write enable

FLASH_OEn

M16 F7 FSM bus flash memory output enable

FLASH_RDYBSYn

L11 B7 FSM bus flash memory ready

FLASH_CLK

L15 Y21 FSM bus flash memory clock

FLASH_CEn

K14 E25 FSM bus flash memory chip enable

FPGA_DATA0

2.5-V

D3 A3 FPGA data

FPGA_DATA1

L1 G9 FPGA data

FPGA_DATA2

J16 H9 FPGA data

FPGA_DATA3

J13 D1 FPGA data

FPGA_DATA4

H16 C2 FPGA data

FPGA_DATA5

H13 AE4 FPGA data

FPGA_DATA6

H15 AE5 FPGA data

FPGA_DATA7

H14 AE10 FPGA data

FPGA_DCLK

C2 B3 FPGA configuration clock

FPGA_CONF_DONE

E3 B1 FPGA configuration done

FPGA_STATUSn

C3 AJ1 FPGA configuration ready

FPGA_CONFIGn

E4 AB9 FPGA configuration active

JTAG_TCK

P3 F2 FPGA JTAG TCK

JTAG_TMS

N4 E1 FPGA JTAG TMS

JTAG_FPGA_TDO

L6 F1 FPGA JTAG TDO

JTAG_EPM2210_TDO

M5 E2 MAX II JTAG TDO

Table 2–5. MAX II CPLD EPM2210 System Controller Device Pin-Out (Part 2 of 4)

Schematic Signal Name

I/O

Standard

EPM2210

Pin Number

EP4CGX15BF14

Pin Number

Description

1 2 ... 12 13 14 15 16 17 18 19 20 21 22 ... 59 60

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