Altera Cyclone IV GX FPGA Development Board Uživatelský manuál stáhnout pdf (Strana 19)

Chapter 2: Board Components 2–11

MAX II CPLD EPM2210 System Controller

May 2013 Altera Corporation Cyclone IV GX FPGA Development Board

Reference Manual

FSM_A24

1.8-V

R8 AK27 FSM bus address

FSM_A25

M9 AF21 FSM bus address

FSM_D0

E9 AK14 FSM bus data

FSM_D1

A9 AE6 FSM bus data

FSM_D2

E7 AG21 FSM bus data

FSM_D3

B7 AE9 FSM bus data

FSM_D4

A6 AK28 FSM bus data

FSM_D5

A8 AD23 FSM bus data

FSM_D6

C7 AG24 FSM bus data

FSM_D7

B6 AB22 FSM bus data

FSM_D8

E8 AE22 FSM bus data

FSM_D9

B8 AJ24 FSM bus data

FSM_D10

D8 Y19 FSM bus data

FSM_D11

D7 AH23 FSM bus data

FSM_D12

A7 AK22 FSM bus data

FSM_D13

C8 AH24 FSM bus data

FSM_D14

B5 Y18 FSM bus data

FSM_D15

A5 AJ13 FSM bus data

HSMA_PSNTn

2.5-V

G5 A25 HSMC port A present LED

HSMB_PSNTn

H2 C26 HSMC port B present LED

MAX_EPCS

G3 — MAX II EPCS memory chip enable

MAX_ERROR

G2 — FPGA configuration error LED

MAX_FACTORY

G4 — FPGA factory configuration LED

MAX_USER

G1 — FPGA user configuration LED

MAX_FAN

1.8-V

B1 — FPGA fan LED

MAX_CSn

L16 B12 MAX II chip select

MAX_OEn

K13 G8 MAX II output enable

MAX_WEn

K15 A9 MAX II write enable

MSEL0

2.5-V

L2 AD7 FPGA MSEL0 configuration mode select

MSEL2

M1 AC7 FPGA MSEL2 configuration mode select

MSEL3

M2 AC8 FPGA MSEL3 configuration mode select

RESET_CONFIGn

1.8-V G16 AF27 Force FPGA configuration push button

SENSE_CSn

2.5-V

F5 — Power monitor chip select

SENSE_SCK

E1 —

Power monitor serial peripheral interface (SPI)

clock

SENSE_SDI

F4 — Power monitor SPI data in

SENSE_SDO

E2 — Power monitor SPI data out

SYS_RESETn

1.8-V J15 AF27 System reset push button

USER_FACTORY

2.5-V N1 — User reset push button

Table 2–5. MAX II CPLD EPM2210 System Controller Device Pin-Out (Part 4 of 4)

Schematic Signal Name

I/O

Standard

EPM2210

Pin Number

EP4CGX15BF14

Pin Number

Description

1 2 ... 14 15 16 17 18 19 20 21 22 23 24 ... 59 60

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