Altera CPRI IP Core Uživatelský manuál Strana 140
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Hodnocené. / 5. Na základě hodnocení zákazníků
7–24 Chapter 7: Software Interface
Ethernet Registers
CPRI MegaCore Function December 2013 Altera Corporation
User Guide
rx_eop
[1] RO
Indicates that the next ready data word contains the end-of-packet
byte.
1’h0
rx_ready
[0] RO
Indicates that at least one 32-bit word of Ethernet data is available in
the Ethernet Rx buffer and ready to be read.
1’h0
Table 7–51. ETH_RX_STATUS—Ethernet Receiver Module Status—Offset: 0x200 (Part 2 of 2)
Field Bits Access Function Default
Table 7–52. ETH_TX_STATUS—Ethernet Transmitter Module Status—Offset: 0x204
Field Bits Access Function Default
RSRV
[31:3] UR0 Reserved.
29'h0
tx_ready_block
[2] RO
Indicates that the Ethernet Tx module is ready to receive an 8-word
block of data.
1’h0
tx_abort
[1] RO Indicates the current Ethernet Tx packet is aborted.
1’h0
tx_ready
[0] RO
Indicates that the Ethernet Tx module is ready to receive at least one
32-bit word of data.
1’h0
Table 7–53. ETH_CONFIG_1—Ethernet Feature Configuration 1—Offset: 0x208 (Part 1 of 2)
Field Bits Access Function Default
RSRV
[31:20] UR0 Reserved.
11'h0
intr_tx_ready_block_en
[19] RW
Indicates an interrupt is generated when
tx_ready_block
is asserted, if
intr_en
and
intr_tx_en
are asserted.
1’h0
intr_tx_abort_en
[18] RW
Indicates an interrupt is generated when
tx_abort
is
asserted, if
intr_en
and
intr_tx_en
are asserted.
1’h0
intr_tx_ready_en
[17] RW
Indicates an interrupt is generated when
tx_ready
is
asserted, if
intr_en
and
intr_tx_en
are asserted.
1’h0
intr_rx_ready_block_en
[16] RW
Indicates an interrupt is generated when
rx_ready_block
is asserted, if
intr_en
and
intr_rx_en
are asserted.
1’h0
intr_rx_ready_end_en
[15] RW
Indicates an interrupt is generated when
rx_ready_end
is
asserted, if
intr_en
and
intr_rx_en
are asserted.
1’h0
intr_rx_abort_en
[14] RW
Indicates an interrupt is generated when
rx_abort
is
asserted, if
intr_en
and
intr_rx_en
are asserted.
1’h0
intr_rx_ready_en
[13] RW
Indicates an interrupt is generated when
rx_ready
is
asserted, if
intr_en
and
intr_rx_en
are asserted.
1’h0
intr_tx_en
[12] RW Ethernet Tx interrupt enable.
1’h0
intr_rx_en
[11] RW Ethernet Rx interrupt enable.
1’h0
intr_en
[10] RW Ethernet global interrupt enable.
1’h0
rx_long_frame_en
[9] RW
Enable reception of Rx Ethernet frames longer than 1536
bytes.
1’h0
rx_preamble_abort_en
[8] RW
Indicates that Rx frames with an illegal preamble nibble
before the SFD are discarded.
1’h0
broadcast_en
[7] RW Enable reception of Ethernet broadcast packets.
1’h0
multicast_flt_en
[6] RW
Enable reception of multicast Ethernet packets allowed by
the hash function.
1’h0
- User Guide 1
- CPRI MegaCore Function 1
- Contents 3
- Chapter 5. Testing Features 4
- ContentsContents v 5
- General Description 8
- CPRI IP Core Features 10
- Device Family Support 11
- MegaCore Verification 12
- Release Information 14
- Installation and Licensing 15
- OpenCore Plus Evaluation 16
- 2. Getting Started 17
- Specifying Parameters 18
- Simulation Files 19
- Simulating the Design 20
- Supporting the Transceivers 21
- Specifying Constraints 21
- 3. Parameter Settings 25
- Operation Mode Parameter 26
- Line Rate Parameter 26
- Enable Autorate Negotiation 27
- Rx Elastic Buffer Depth 27
- Include MAC Block 28
- Include HDLC Block 29
- Mapping Mode 29
- Application Layer Parameters 30
- Words” on page 4–42 32
- 4. Functional Description 33
- Architecture Overview 34
- CPRI IP Core Clocks 35
- Clocking Structure 36
- Notes to Table 4–2: 42
- Reset Requirements 43
- MegaCore 44
- Function 44
- MAP Interface Mapping Modes 45
- Basic AxC Mapping Mode 46
- MAP Interface 47
- Note to Table 4–5: 49
- Note to Table 4–6: 49
- Advanced AxC Mapping Modes 50
- MAP Receiver Interface 50
- Notes to Table 4–7: 51
- MAP Receiver in FIFO Mode 52
- MAP Transmitter Interface 56
- Notes to Table 4–10: 57
- MAP Transmitter in FIFO Mode 58
- Auxiliary Interface 62
- AUX Receiver Module 63
- Avalon-ST 32-bit interface 64
- AUX Transmitter Module 66
- Note to Figure 4–19: 67
- MII Transmitter 70
- MII Receiver 71
- CPU Interface 73
- Control Word Order 78
- Transmitting Ethernet Traffic 80
- Receiving Ethernet Traffic 81
- Accessing the HDLC Channel 82
- Note to Table 4–15: 83
- Features 84
- Physical Layer Architecture 84
- Receiver 85
- High-Speed Transceiver 86
- Rx Elastic Buffer 86
- Descrambling 87
- Frame Synchronization 87
- Alarm Indications 88
- Reset Control Word 89
- Transmitter 90
- Scrambling 91
- Tx Elastic Buffer 91
- External Loopback 93
- CPRI IP Core 93
- Internal Reverse Loopback 94
- Physical Layer Loopback Mode 94
- (1) (2) (3) 96
- MAP Receiver Signals 99
- 6–2 Chapter 6: Signals 100
- MAP Interface Signals 100
- MAP Transmitter Signals 101
- 6–4 Chapter 6: Signals 102
- Auxiliary Interface Signals 103
- AUX Receiver Signals 104
- AUX Transmitter Signals 105
- 6–8 Chapter 6: Signals 106
- Extended Rx Status Signals 107
- CPRI MII Receiver Signals 108
- CPRI MII Transmitter Signals 108
- CPU Interface Signals 109
- CPRI Data Signals 110
- Layer 1 Error Signal 111
- Autorate Negotiation Signals 111
- 6–14 Chapter 6: Signals 112
- Physical Layer Signals 112
- Transceiver Signals 113
- 6–16 Chapter 6: Signals 114
- Note to Table 6–14: 115
- 6–18 Chapter 6: Signals 116
- 7. Software Interface 117
- Note to Table 7–5: 119
- CPRI_HW_RESET 123
- register, refer to “Reset 123
- Requirements” on page 4–11 123
- Note to Table 7–13: 124
- Note to Table 7–16: 125
- Note to Table 7–17: 126
- Note to Table 7–20: 126
- Notes to Table 7–21: 127
- Notes to Table 7–28: 130
- Notes to Table 7–29: 130
- Note to Table 7–32: 133
- Note to Table 7–33: 133
- Note to Table 7–34: 133
- Note to Table 7–35: 134
- Note to Table 7–36: 134
- Notes to Table 7–37: 135
- Notes to Table 7–38: 135
- Notes to Table 7–39: 136
- Notes to Table 7–40: 136
- Note to Table 7–45: 137
- Ethernet Registers 138
- HDLC Registers 143
- Note to Figure 8–1: 150
- Test Sequence 151
- Running the Testbench 153
- A. Initialization Sequence 155
- Negotiation 157
- Notes for Figure B–1: 158
- Running Autorate Negotiation 159
- Notes to Table C–3: 167
- D. Advanced AxC Mapping Modes 173
- Fifteen-Bit Width Mode 175
- Sixteen-Bit Width Mode 176
- Note to Figure D–2: 177
- Delay Requirements 179
- RE SlaveREC Master 180
- Rx Path Delay 181
- Most CPRI IP Core Variations 181
- Single-Hop Delay Measurement 182
- Notes to Table E–1: 183
- Notes to Table E–2: 184
- Notes to Table E–3: 186
- Arria V GT 9.8 Gbps 188
- Notes to Table E–4: 189
- Tx Path Delay 190
- Note to Table E–6: 192
- T_txv_TX 194
- in Figure E–1 on page E–2 194
- Round-Trip Delay 196
- Round-Trip Cable Delay 196
- Families 202
- Round-Trip Delay Calculation 205
- Multi-Hop Delay Measurement 206
- Additional Information 213
- Document Revision History 214
- How to Contact Altera 218
- Typographic Conventions 218
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