Altera Arria V SoC Development Board Uživatelský manuál stáhnout pdf (Strana 57)

Chapter 2: Board Components 2–49

Memory

July 2014 Altera Corporation Arria V SoC Development Board

Reference Manual

DDR3_HPS_CLK_N

B10 1.5-V SSTL Class I Differential output clock

DDR3_HPS_CSN

H9 1.5-V SSTL Class I Chip select

DDR3_HPS_DM0

C6 1.5-V SSTL Class I Write mask byte lane

DDR3_HPS_DM1

E4 1.5-V SSTL Class I Write mask byte lane

DDR3_HPS_DQ0

D7 1.5-V SSTL Class I Data bus

DDR3_HPS_DQ1

C7 1.5-V SSTL Class I Data bus

DDR3_HPS_DQ2

R10 1.5-V SSTL Class I Data bus

DDR3_HPS_DQ3

G7 1.5-V SSTL Class I Data bus

DDR3_HPS_DQ4

A6 1.5-V SSTL Class I Data bus

DDR3_HPS_DQ5

A7 1.5-V SSTL Class I Data bus

DDR3_HPS_DQ6

L6 1.5-V SSTL Class I Data bus

DDR3_HPS_DQ7

D6 1.5-V SSTL Class I Data bus

DDR3_HPS_DQ8

H6 1.5-V SSTL Class I Data bus

DDR3_HPS_DQ9

G6 1.5-V SSTL Class I Data bus

DDR3_HPS_DQ10

N8 1.5-V SSTL Class I Data bus

DDR3_HPS_DQ11

G5 1.5-V SSTL Class I Data bus

DDR3_HPS_DQ12

A4 1.5-V SSTL Class I Data bus

DDR3_HPS_DQ13

A5 1.5-V SSTL Class I Data bus

DDR3_HPS_DQ14

R9 1.5-V SSTL Class I Data bus

DDR3_HPS_DQ15

F4 1.5-V SSTL Class I Data bus

DDR3_HPS_DQS_P0

Differential 1.5-V

SSTL Class I

Data strobe P byte lane 1

DDR3_HPS_DQS_N0

Differential 1.5-V

SSTL Class I

Data strobe P byte lane 0

DDR3_HPS_DQS_P1

Differential 1.5-V

SSTL Class I

Data strobe N byte lane 1

DDR3_HPS_DQS_N1

Differential 1.5-V

SSTL Class I

Data strobe N byte lane 0

DDR3_HPS_ODT

H7 1.5-V SSTL Class I On-die termination enable

DDR3_HPS_RASN

G8 1.5-V SSTL Class I Row address select

DDR3_HPS_RESETN

E3 1.5-V SSTL Class I Reset

DDR3_HPS_WEN

J8 1.5-V SSTL Class I Write enable

DDR3_HPS_ZQ

— 1.5-V SSTL Class I ZQ impedance calibration

Table 2–28. DDR3 SDRAM Pin Assignments, Schematic Signal Names, and Functions (Part 5 of 5)

Board

Reference

Schematic

Signal Name

Arria V SoC Pin

Number

I/O Standard Description

1 2 ... 52 53 54 55 56 57 58 59 60 61 62 ... 69 70

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