Altera Arria V SoC Development Board Uživatelský manuál stáhnout pdf (Strana 55)

Chapter 2: Board Components 2–47

Memory

July 2014 Altera Corporation Arria V SoC Development Board

Reference Manual

DDR3 x16 (U44)

DDR3_HPS_A0

N9 1.5-V SSTL Class I Address bus

DDR3_HPS_A1

M9 1.5-V SSTL Class I Address bus

DDR3_HPS_A2

N10 1.5-V SSTL Class I Address bus

DDR3_HPS_A3

M10 1.5-V SSTL Class I Address bus

DDR3_HPS_A4

A8 1.5-V SSTL Class I Address bus

DDR3_HPS_A5

B7 1.5-V SSTL Class I Address bus

DDR3_HPS_A6

B9 1.5-V SSTL Class I Address bus

DDR3_HPS_A7

A9 1.5-V SSTL Class I Address bus

DDR3_HPS_A8

D9 1.5-V SSTL Class I Address bus

DDR3_HPS_A9

C10 1.5-V SSTL Class I Address bus

DDR3_HPS_A10

K7 1.5-V SSTL Class I Address bus

DDR3_HPS_A11

J7 1.5-V SSTL Class I Address bus

DDR3_HPS_A12

F9 1.5-V SSTL Class I Address bus

DDR3_HPS_A13

E9 1.5-V SSTL Class I Address bus

DDR3_HPS_A14

D11 1.5-V SSTL Class I Address bus

DDR3_HPS_BA0

L7 1.5-V SSTL Class I Bank address bus

DDR3_HPS_BA1

C9 1.5-V SSTL Class I Bank address bus

DDR3_HPS_BA2

D8 1.5-V SSTL Class I Bank address bus

DDR3_HPS_CASN

G9 1.5-V SSTL Class I Row address select

DDR3_HPS_CKE

R8 1.5-V SSTL Class I Column address select

DDR3_HPS_CLK_P

A11 1.5-V SSTL Class I Differential output clock

DDR3_HPS_CLK_N

B10 1.5-V SSTL Class I Differential output clock

DDR3_HPS_CSN

H9 1.5-V SSTL Class I Chip select

DDR3_HPS_DM2

D3 1.5-V SSTL Class I Write mask byte lane

DDR3_HPS_DM3

D1 1.5-V SSTL Class I Write mask byte lane

DDR3_HPS_DQ16

J5 1.5-V SSTL Class I Data bus

DDR3_HPS_DQ17

K5 1.5-V SSTL Class I Data bus

DDR3_HPS_DQ18

N7 1.5-V SSTL Class I Data bus

DDR3_HPS_DQ19

F3 1.5-V SSTL Class I Data bus

DDR3_HPS_DQ20

H3 1.5-V SSTL Class I Data bus

DDR3_HPS_DQ21

J4 1.5-V SSTL Class I Data bus

DDR3_HPS_DQ22

M5 1.5-V SSTL Class I Data bus

DDR3_HPS_DQ23

C3 1.5-V SSTL Class I Data bus

DDR3_HPS_DQ24

A2 1.5-V SSTL Class I Data bus

DDR3_HPS_DQ25

A3 1.5-V SSTL Class I Data bus

DDR3_HPS_DQ26

P7 1.5-V SSTL Class I Data bus

DDR3_HPS_DQ27

C1 1.5-V SSTL Class I Data bus

Table 2–28. DDR3 SDRAM Pin Assignments, Schematic Signal Names, and Functions (Part 3 of 5)

Board

Reference

Schematic

Signal Name

Arria V SoC Pin

Number

I/O Standard Description

1 2 ... 50 51 52 53 54 55 56 57 58 59 60 ... 69 70

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