Altera 50G Interlaken MegaCore Function Uživatelský manuál Strana 87
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RX Out-of-Band Flow Control Signals
The receive out-of-band flow control interface receives input flow-control clock, data, and sync signals
and sends out calendar and status information. The RX Out-of-Band Flow Control Interface Signals table
describes the receive out-of-band flow control interface signals specified in the Interlaken Protocol Specifi‐
cation, Revision 1.2. The RX Out-of-Band Flow Control Block Signals for Application Use describes the
signals on the application side of the RX out-of-band flow control block.
Table 10-4: RX Out-of-Band Flow Control Interface Signals
Signal Name Direction Width
(Bits)
Description
fc_clk Input 1 Input reference clock from an upstream out-of-band TX block. This
signal clocks the fc_data and fc_sync signals. You must connect this
signal to a device pin.
fc_data Input 1 Input serial data pin from an upstream out-of-band TX block. You
must connect this signal to a device pin.
fc_sync Input 1 Input sync control pin from an upstream out-of-band TX block. You
must connect this signal to a device pin.
Table 10-5: RX Out-of-Band Flow Control Block Signals for Application Use
Signal Name Direction Width
(Bits)
Description
sys_clk Input 1 Reference clock for capturing RX calendar, lane status,
and link status. Frequency must be at least double the
frequency of the TX fc_clk input clock.
sys_arst Input 1 Asynchronous reset for the out-of-band RX block.
status_update Output 1 Indicates a new value without CRC4 errors is present on
at least one of lane_status or link_status in the
current sys_clk cycle. The value is ready to be read by
the application logic.
lane_status Output Number of
Lanes
Lane status bits received from an upstream out-of-band
TX block on fc_data. Width is the number of lanes.
link_status Output 1 Link status bit received from an upstream out-of-band
TX block on fc_data.
status_error Output 1 Indicates corrupt lane or link status. A new value is
present on at least one of lane_status or link_status
in the current sys_clk cycle, but the value has at least
one CRC4 error.
10-4
RX Out-of-Band Flow Control Signals
UG-01140
2015.05.04
Altera Corporation
Out-of-Band Flow Control in the 50G Interlaken MegaCore Function
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- 101 Innovation Drive 1
- San Jose, CA 95134 1
- Contents 2
- About This MegaCore Function 3
- Device Family Support 6
- IP Core Verification 7
- Device Speed Grade Support 8
- Release Information 8
- Altera IP Core Release Notes 9
- OpenCore Plus IP Evaluation 10
- UG-01140 11
- 2015.05.04 11
- Related Information 12
- 10 variation 13
- Pin Assignments 15
- Send Feedback 16
- Altera Corporation 16
- Adding the External PLL 21
- 50G Interlaken IP Core 22
- Meta Frame Length in Words 24
- Number of Calendar Pages 25
- TX Scrambler Seed 25
- Transfer Mode Selection 25
- Functional Description 27
- Management Interface 28
- High Level Block Diagram 30
- IP Core Reset 31
- Interleaved and Packet Modes 33
- 50G Interlaken IP Core TX MAC 40
- 50G Interlaken IP Core TX PCS 40
- 50G Interlaken IP Core TX PMA 40
- 50G Interlaken IP Core RX PMA 45
- 50G Interlaken IP Core RX PCS 45
- 50G Interlaken IP Core RX MAC 45
- Signal Name Direction Width 47
- Description 47
- Device Dependent Signals 60
- Offset Name R/W Description 63
- Example Design 68
- Top Testbench 68
- Testbench Simulation Behavior 70
- Internal Serial Loopback Mode 72
- External Loopback Mode 72
- CRC32 Error Injection 78
- Advanced Parameter Settings 79
- Counter Reset Bits 80
- Include Temp Sense 80
- RXFIFO Address Width 80
- Use ATX or CMU PLL 82
- Lane Profile 82
- MegaCore Function 84
- Ethernet Traffic 89
- Additional Information 91
- How to Contact Altera 93
- Typographic Conventions 93
- Visual Cue Meaning 94
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