Altera 50G Interlaken MegaCore Function Uživatelský manuál Strana 78
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Related Information
• 50G Interlaken IP Core Register Map on page 6-1
Describes the PRBS status registers and the soft reset register.
• Arria 10 Transceiver Reconfiguration Interface Signals on page 5-15
Describes the interface to program the Arria 10 hard PCS registers, including the information you
need to address the registers for each individual lane.
• 50G Interlaken IP Core Management Interface on page 5-12
Describes the interface to program the 50G Interlaken IP core registers, including the RESET register.
• PRBS Generation and Validation on page 8-2
Lists the supported PRBS polynomials.
• Arria 10 Transceiver PHY User Guide
Information about the Arria 10 transceiver reconfiguration interface.
• Arria 10 Transceiver Registers
Information about the Arria 10 transceiver registers.
CRC32 Error Injection
The 50G Interlaken IP core supports the injection of CRC32 errors on the Interlaken link for validation of
the Interlaken link partner's error handling, and for validation of this IP core's error handling in a
loopback configuration. Variations that target an Arria V or Stratix V device require that you first enable
the feature in the hard PCS; variations that target an Arria 10 device do not require this step.
To enable the CRC32 error injection feature in your 50G Interlaken IP core that targets an Arria V or
Stratix V device, set the value of bit [15] of the hard PCS register at offset 0x138 (offset 0xC from the hard
PCS base address of 0x12C) to the value of 1. Ensure you set the register bit using a read-modify-write
register access sequence, to avoid modifying the other register fields. This step is not necessary in
50G Interlaken IP core devices that target an Arria 10 device, because CRC32 error injection is enabled by
default in these variations.
For instructions to program the hard PCS registers in Arria V and Stratix V devices, refer to the Native
PHY IP Core chapter for your target device family and to the Transceiver Reconfiguration Controller
chapter of the Altera Transceiver PHY IP Core User Guide.
After you enable the IP core to inject CRC32 errors in the output to the Interlaken link, you can turn on
the feature using the 50G Interlaken IP core CRC32_ERR_INJECT register. You must maintain each register
bit at the value of 1 for the duration of a Meta Frame, at least, to ensure that the IP core transmits at least
one CRC32 error on the corresponding lane.
After your testing is complete, in Arria V and Stratix V devices, you must reset the hard PCS register bit to
its default value of zero to enable normal operation.
The 50G Interlaken IP core CRC32 error injection feature does not keep a count of the errors injected.
Related Information
50G Interlaken IP Core Register Map on page 6-1
Describes the CRC32_ERR_INJECT register.
Altera Transceiver PHY IP Core User Guide
UG-01140
2015.05.04
CRC32 Error Injection
8-7
50G Interlaken IP Core Test Features
Altera Corporation
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- 101 Innovation Drive 1
- San Jose, CA 95134 1
- Contents 2
- About This MegaCore Function 3
- Device Family Support 6
- IP Core Verification 7
- Device Speed Grade Support 8
- Release Information 8
- Altera IP Core Release Notes 9
- OpenCore Plus IP Evaluation 10
- UG-01140 11
- 2015.05.04 11
- Related Information 12
- 10 variation 13
- Pin Assignments 15
- Send Feedback 16
- Altera Corporation 16
- Adding the External PLL 21
- 50G Interlaken IP Core 22
- Meta Frame Length in Words 24
- Number of Calendar Pages 25
- TX Scrambler Seed 25
- Transfer Mode Selection 25
- Functional Description 27
- Management Interface 28
- High Level Block Diagram 30
- IP Core Reset 31
- Interleaved and Packet Modes 33
- 50G Interlaken IP Core TX MAC 40
- 50G Interlaken IP Core TX PCS 40
- 50G Interlaken IP Core TX PMA 40
- 50G Interlaken IP Core RX PMA 45
- 50G Interlaken IP Core RX PCS 45
- 50G Interlaken IP Core RX MAC 45
- Signal Name Direction Width 47
- Description 47
- Device Dependent Signals 60
- Offset Name R/W Description 63
- Example Design 68
- Top Testbench 68
- Testbench Simulation Behavior 70
- Internal Serial Loopback Mode 72
- External Loopback Mode 72
- CRC32 Error Injection 78
- Advanced Parameter Settings 79
- Counter Reset Bits 80
- Include Temp Sense 80
- RXFIFO Address Width 80
- Use ATX or CMU PLL 82
- Lane Profile 82
- MegaCore Function 84
- Ethernet Traffic 89
- Additional Information 91
- How to Contact Altera 93
- Typographic Conventions 93
- Visual Cue Meaning 94
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