Altera 40-Gbps Ethernet MAC and PHY MegaCore Function Uživatelský manuál Strana 39
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File Names Description
run_vcs.sh
The Synopsys VCS script to run the testbench.
run_ncsim.sh
The Cadence NCSim script to run the testbench.
Figure 2-5: Typical 40GbE Traffic on the Avalon-ST Interface Using the Four- to Two-Word Adapters
Shows typical traffic from the simulation testbench created using the <instance_name>_example/
alt_e40_e100/example_testbench/run_vsim.do script in ModelSim.
Note: Client logic must maintain the l4_tx_valid signal asserted while asserting SOP, through the
assertion of EOP. Client logic should not pull this signal low during a packet transmission.
l4_tx_data[255:0]
l4_tx_empty[4:0]
l4_tx_startofpacket
l4_tx_endofpacket
l4_tx_ready
l4_tx_valid
l4_rx_data[255:0]
l4_rx_startofpacket
l4_rx_endofpacket
l4_rx_valid
l4_rx_empty[4:0]
B8 . B8 . B8 . B87B0031B8 . 57 . 57 . 57 . 57 . 573500 . 5735004 . 57350055573500545735005357
00 02 00 01
65F300 .. 65F301 . 65F301 . 65F301 . FA . FAAB00 . FAAB00 . FAAB00 . FAAB00 . 61 . 61A000 .
14
1D
1 2
3 4
6 8 975
The markers in the figure show the following sequence of events:
1. At marker 1, the application asserts l4_tx_startofpacket, indicating the beginning of a TX packet.
2. At marker 2, the application asserts l4_tx_endofpacket, indicating the end of the TX packet. The
value on l4_tx_empty[4:0] indicates that the 2 least significant bytes of the last data cycle are empty.
3. At marker 3, the IP core asserts l4_rx_startofpacket, indicating the beginning of an RX packet. A
second transfer has already started on the TX bus.
4. At marker 4, the 40GbE IP core deasserts l4_rx_valid, indicating that the IP core does not have new
valid data to send to the client on l4_rx_data[255:0]. l4_rx_data[255:0] remains valid and
unchanged for a second cycle.
5. A marker 5, the 40GbE IP core asserts l4_rx_valid, indicating that the it has valid data to send to the
client on l4_rx_data[255:0].
6. At marker 6, the 40GbE IP core deasserts l4_rx_valid, indicating that it does not have new valid data
to send to the client on l4_rx_data[255:0]. l4_rx_data[255:0] remains unchanged for a second
cycle.
UG-01088
2014.12.15
Testbenches with Adapters
2-17
Getting Started
Altera Corporation
Send Feedback
- MegaCore Function User Guide 1
- Contents 2
- PHY MegaCore Function 4
- 40- or 100-GbE MAC 5
- Device Family Support 7
- IP Core Verification 9
- Simulation Environment 10
- Hardware Testing 10
- Module ALMs Logic Registers 11
- Release Information 21
- Item Description 22
- Getting Started 23
- OpenCore Plus IP Evaluation 24
- IP Core Parameters 25
- Parameter Type Range Default 28
- Parameter Description 28
- Simulating the IP Core 32
- Pin Assignments 33
- 40-100GbE IP Core Testbenches 36
- Testbenches with Adapters 37
- File Names Description 38
- Testbenches without Adapters 40
- Initializing the IP Core 46
- High Level System Overview 49
- 40-100GbE IP Core TX Datapath 50
- Address Insertion 51
- Length/Type Field Processing 52
- Frame Padding 52
- Client Interface 53
- Data Bus Width (Bits) 53
- 40GbE IP Core 100GbE IP Core 53
- 40-100GbE IP Core RX Datapath 67
- RX CRC Forwarding 69
- Address Checking 71
- Inter‑Packet Gap 71
- Pause Ignore 71
- Name Direction Description 73
- 100GbE CAUI–4 PHY 79
- Pause Transmission Logic 82
- Statistics Counters Interface 86
- Name Signal 87
- Direction 87
- Description 87
- Control Data Description 89
- Lane to Lane Deskew Interface 90
- MII Control 91
- MII Data 91
- PCS BER Monitor 92
- Control and Status Interface 98
- Signal Name Description 100
- UG-01088 101
- 2014.12.15 101
- Related Information 102
- Send Feedback 103
- Altera Corporation 103
- Functional Description 103
- Software Interface: Registers 123
- Register Description 124
- 40-100GbE IP Core Registers 126
- Address Name Applicable 128
- Device(s) 128
- Bit Description HW Reset 128
- Bits Description HW Reset 130
- Lock Status Registers 131
- Bit Error Flag Registers 133
- PCS Hardware Error Register 134
- BER Monitor Register 134
- Test Mode Register 135
- Test Pattern Counter Register 135
- MAC and PHY Reset Registers 136
- PCS‑VLANE Registers 138
- PRBS Registers 139
- 40GBASE-KR4 Registers 139
- Pause Registers 149
- MAC Hardware Error Register 151
- CRC Configuration Register 152
- MAC Address Registers 154
- Statistics Registers 155
- PMD Registers 163
- MDIO Registers 164
- Ethernet Glossary 166
- Term Definition 167
- Subscribe 169
- Core v12.0 Release 173
- 10GBASE-KR Registers 174
- Bit R/W Name Description 175
- Additional Information 190
- Date ACDS 191
- at offset 0x127), described 193
- How to Contact Altera 198
- Typographic Conventions 198
- Visual Cue Meaning 199
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