Altera 40-Gbps Ethernet MAC and PHY MegaCore Function Uživatelský manuál Strana 147

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Address Name Bit Description HW Reset
Value
Access
0x102
MAC_CMD_
config
[4] When set to 1, the transmit CRC FIFO is
cleared. Used for hardware diagnostics. Not
required for normal operation. To clear this
register bit, write a 0.
1’b0 RW
[3] When set to 1, the statistics counters are
reset. This register is self-clearing.
1’b0 RW
[2] When set to 1, statistics collection is paused.
The underlying counters continue to operate,
but the readable values reflect a snapshot at
the time the pause flag was activated. Write a
0 to release.
1’b0 RW
[1:0] Allows you to override normal transmission
for hardware diagnostic purposes: The
following patterns are defined:
2’b00 / 2’b10–normal operation (default)
2’b01–Send a small repeating loop of
random content frames
2’b11–Send idles
2’b00 RW
3-100
MAC Configuration and Filter Registers
UG-01088
2014.12.15
Altera Corporation
Functional Description
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