Altera 100G Interlaken MegaCore Function Uživatelský manuál Strana 60
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Signal Name Direction Width
(Bits)
Description
tx_serial_clk
Input
NUM_
LANES–
Clocks for the individual transceiver channels in
100G Interlaken IP core variations that target an Arria
10 device.
clk_tx_common Output 1 PCS common lane clock driven by the SERDES
transmit PLL. The clock rate is the lane rate divided
by 40 bits. The clk_tx_common frequency is
156.25 MHz for 6.25 Gbps, 257.8 MHz for
10.3125 Gbps, and 312.5 MHz for 12.5 Gbps per lane.
clk_rx_common Output 1 Master recovered lane clock. The Interlaken specifica‐
tion requires all incoming lanes to run at the same
frequency.
tx_usr_clk Input 1 Transmit side user data interface clock. To achieve
100 Gbps Ethernet traffic throughput, you must run
this clock at one of the following minimum frequen‐
cies:
• 225 MHz in dual segment mode, 12-lane variations
• 300 MHz in single segment mode and in 24-lane
variations
rx_usr_clk Input 1 Receive side user data interface clock. To achieve 100
Gbps Ethernet traffic throughput, you must run this
clock at one of the following minimum frequencies:
• 225 MHz in dual segment mode, 12-lane variations
• 300 MHz in single segment mode and in 24-lane
variations
mm_clk
Input
1
Management clock. Clocks the register accesses. It is
also used for clock rate monitoring and some analog
calibration procedures. You must run this clock at a
frequency in the range of 100 MHz–125 MHz.
reconfig_clk
Input
1 Clocks the Arria 10 transceiver reconfiguration
interface. This clock is available only in IP core
variations that target an Arria 10 device. You should
run this clock at a frequency of 100 MHz.
Related Information
Performance and Fmax Requirements for 100G Ethernet Traffic on page 11-1
Explains the tx_usr_clk and rx_usr_clk frequency requirements.
5-2
100G Interlaken IP Core Clock Interface Signals
UG-01128
2015.05.04
Altera Corporation
100G Interlaken MegaCore Function Signals
Send Feedback
- 101 Innovation Drive 1
- San Jose, CA 95134 1
- Contents 2
- About This MegaCore Function 3
- Device Family Support 6
- IP Core Verification 7
- Device Speed Grade Support 9
- Release Information 9
- Altera IP Core Release Notes 10
- OpenCore Plus IP Evaluation 11
- - HDL synthesis file 13
- 10 variation 14
- Pin Assignments 16
- Adding the External PLL 22
- 100G Interlaken IP Core 23
- Number of Lanes 25
- Meta Frame Length in Words 26
- Data Rate 26
- Enable M20K ECC Support 28
- Include Diagnostic Features 28
- Number of Calendar Pages 29
- TX Scrambler Seed 29
- Transfer Mode Selection 30
- Data Format 30
- Functional Description 31
- Management Interface 32
- High Level Block Diagram 34
- IP Core Reset 35
- Interleaved and Packet Modes 37
- Dual Segment Mode 38
- M20K ECC Support 40
- Device Dependent Signals 72
- Offset Name R/W Description 76
- Example Design 82
- Top Testbench 82
- Testbench Simulation Behavior 83
- Simulating the Example Design 84
- Internal Serial Loopback Mode 86
- External Loopback Mode 87
- CRC32 Error Injection 92
- CRC24 Error Injection 93
- Advanced Parameter Settings 94
- RXFIFO Address Width 95
- Subscribe 98
- UG-01128 100
- 2015.05.04 100
- Signal Name Direction Width 102
- Description 102
- Related Information 102
- Ethernet Traffic 103
- Altera Corporation 105
- Send Feedback 105
- Additional Information 106
- Date ACDS 107
- Changes Made 107
- How to Contact Altera 110
- Typographic Conventions 110
- Visual Cue Meaning 111
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