Altera Ethernet Blaster Communications Cable Specifikace

Cyclone V Device HandbookVolume 1: Device Interfaces and Integration101 Innovation DriveSan Jose, CA 95134www.altera.comCV-5V22013.11.12SubscribeSend

1Logic Array Blocks and Adaptive Logic Modulesin Cyclone V Devices2013.05.06CV-52001SubscribeSend FeedbackThis chapter describes the features of the l

VTT(V)(Board TerminationVoltage)VREF(V)(Input RefVoltage)VCCPD(V)(Pre-DriverVoltage)VCCIO(V)I/O StandardOutputInput(10)Typically does notrequire board

If the input signal is 3.0 V or 3.3 V, Altera recommends that you use a clamping diode on the I/Opins.Note:Related InformationI/O Standards Voltage Le

Examples:• An I/O bank can support SSTL-18 inputs and outputs, and 1.8 V inputs and outputs with a 1.8 V VCCIOand a 0.9 V VREF.• An I/O bank can suppo

Table 5-11: Reference Clock Pin for I/O Bank Without Dedicated Reference Clock PinReference Clock Pin I/O BankData Channel I/O BankMember CodeDevice V

Both corner PLLs can drive duplex channels in the same I/O bank if the channels that are driven by eachPLL are not interleaved. You do not require sep

LVDS Interface with External PLL ModeThe MegaWizard Plug-In Manager provides an option for implementing the LVDS interface with the UseExternal PLL op

Related InformationLVDS SERDES Transmitter/Receiver (ALTLVDS_RX/TX) Megafunction User GuideMore information about the different clocking requirement f

Connection between Altera_PLL and ALTLVDSFigure 5-4: LVDS Interface with the Altera_PLL MegafunctionThis figure shows the connections between the Alte

Guideline: Ensure Compatible VCCIOand VCCPDVoltage in the Same BankWhen planning I/O bank usage for Cyclone V devices, you must ensure the VCCIOvoltag

Guideline: Adhere to the LVDS I/O Restrictions and Differential Pad Placement RulesFor Cyclone V LVDS applications, adhere to these guidelines to avoi

Figure 1-1: LAB Structure and Interconnects Overview in Cyclone V DevicesThis figure shows an overview of the Cyclone V LAB and MLAB structure with th

Figure 5-6: I/0 Banks for Cyclone V GX and GT DevicesBank 7ABank 6ATransceiver BlockBank 8ABank 5BBank 5ABank 4ABank 3BBank 3AFigure 5-7: I/0 Banks fo

Related Information• Modular I/O Banks for Cyclone V E Devices on page 5-21• Modular I/O Banks for Cyclone V GX Devices on page 5-22• Modular I/O Bank

Table 5-15: Modular I/O Banks for Cyclone V E A5, A7, and A9 Devices—PreliminaryA9A7A5Member CodeF896F672F484U484F896F672F484U484M484F484U484M383Packa

Table 5-17: Modular I/O Banks for Cyclone V GX C7 and C9 Devices—PreliminaryC9C7Member CodeF1152F896F672F484U484F896F672F484U484M484Package48321616163

Table 5-19: Modular I/O Banks for Cyclone V GT D9 Devices—PreliminaryD9Member CodeF1152F896F672F484U484Package48321616163AI/O Bank48483232323B96808048

A6A5A4A2Member CodeF896U672U484F896U672U484U672U484U672U484Package191919191919191919197AHPSColumnI/OBank222221222221222122217B12128121281281287C141414

Related Information• I/O Banks Locations in Cyclone V Devices on page 5-19• Guideline: Use the Same VCCPDfor All I/O Banks in a Group on page 5-17Prov

I/O Buffer and Registers in Cyclone V DevicesI/O registers are composed of the input path for handling data from the pin to the core, the output path

Programmable IOE Features in Cyclone V DevicesTable 5-24: Summary of Supported Cyclone V Programmable IOE Features and SettingsSupported in HPS I/O(So

Programmable Current StrengthYou can use the programmable current strength to mitigate the effects of high signal attenuation that iscaused by a long

Figure 1-2: LAB and MLAB Structure for Cyclone V DevicesMLABLABLUT-Based-32 x 2Simple Dual-Port SRAMLUT-Based-32 x 2Simple Dual-Port SRAMLUT-Based-32

Programmable Output Slew-Rate ControlThe programmable output slew-rate control in the output buffer of each regular- and dual-function I/O pinallows y

Programmable Pre-EmphasisThe VODsetting and the output impedance of the driver set the output current limit of a high-speedtransmission signal. At a h

Figure 5-11: Differential VODThis figure shows the VODof the differential LVDS output.Single-Ended WaveformPositive Channel (p)Negative Channel (n)Gro

Bus-Hold CircuitryEach I/O pin provides an optional bus-hold feature that is active only after configuration. When the deviceenters user mode, the bus

• RSOCT with Calibration in Cyclone V Devices on page 5-35• RTOCT with Calibration in Cyclone V Devices on page 5-37• LVDS Input RDOCT in Cyclone V De

Uncalibrated OCT (Output)I/O StandardRS(Ω)25Differential SSTL-15 Class II50Differential 1.8 V HSTL Class I25Differential 1.8 V HSTL Class II50Differen

Calibrated OCT (Output)I/O StandardRZQ (Ω)RS(Ω)(11)10025/502.5 V LVCMOS10025/501.8 V LVCMOS10025/501.5 V LVCMOS10025/501.2 V LVCMOS10050SSTL-2 Class I

Calibrated OCT (Output)I/O StandardRZQ (Ω)RS(Ω)(11)24034, 40SSTL-12524034, 40, 48, 60, 80HSUL-1210025, 50Differential SSTL-1524034, 4024034, 40Differe

Table 5-31: Selectable I/O Standards for RTOCT With CalibrationThis table lists the input termination settings for calibrated OCT on different I/O sta

Calibrated OCT (Input)I/O StandardRZQ (Ω)RT(Ω)(12)24020, 30, 40, 60, 120Differential SSTL-125The RTOCT calibration circuit compares the total impedanc

Figure 1-3: LAB Fast Local and Direct Link Interconnects for Cyclone V DevicesMLABALMs ALMsLABFast LocalInterconnectDirect Link Interconnect fromLeft

Figure 5-15: Dynamic RTOCT in Cyclone V DevicesTransmitterReceiver50 Ω100 Ω100 Ω50 ΩGNDTransmitter ReceiverFPGA OCT FPGA OCTZ0= 50 ΩVCCIO100 Ω100 ΩGND

OCT Calibration Block in Cyclone V DevicesYou can calibrate the OCT using any of the available four OCT calibration blocks for each device. Eachcalibr

I/O banks that do not have calibration blocks share the calibration blocks in the I/O banks that havecalibration blocks.All I/O banks support OCT cali

• Dynamic Calibrated On-Chip Termination (ALTOCT) Megafunction User GuideProvides more information about the OCT calibration block.External I/O Termin

External Termination SchemeI/O StandardDifferential HSTL I/O Standard TerminationDifferential 1.8 V HSTL Class IDifferential 1.8 V HSTL Class IIDiffer

Figure 5-19: SSTL I/O Standard TerminationThis figure shows the details of SSTL I/O termination on Cyclone V devices.Transmitter Receiver50 Ω25 Ω25 ΩS

Figure 5-20: HSTL I/O Standard TerminationThis figure shows the details of HSTL I/O termination on the Cyclone V devices.Transmitter Receiver50 ΩVREFV

Figure 5-21: Differential SSTL I/O Standard TerminationThis figure shows the details of Differential SSTL I/O termination on Cyclone V devices.Transmi

Figure 5-23: LVDS and SLVS I/O Standard TerminationThis figure shows the LVDS and SLVS I/O standards termination. The on-chip differential resistor is

Figure 5-24: Emulated LVDS, RSDS, or Mini-LVDS I/O Standard TerminationThe output buffers, as shown in this figure, are available in all I/O banks. RS

Figure 1-4: LAB-Wide Control Signals for Cyclone V DevicesThis figure shows the clock sources and clock enable signals in a LAB.Dedicated RowLAB Clock

Figure 5-25: Resistor Network CalculationAltera recommends that you perform additional simulations with IBIS or SPICE models to validatethat the custo

Figure 5-27: LVPECL DC-Coupled TerminationZ0= 50 ΩZ0= 50 Ω100 ΩLVPECLOutput BufferLVPECLInput BufferFor information about the VICMspecification, refer

Figure 5-28: High-Speed Differential I/O Locations in Cyclone V E A2 and A4 DevicesFPGA Fabric(Logic Elements, DSP,Embedded Memory,Clock Networks)Gene

Figure 5-31: High-Speed Differential I/O Locations in Cyclone V SE A2, A4, A5, and A6 DevicesFPGA Fabric(Logic Elements, DSP,Embedded Memory,Clock Net

Figure 5-33: LVDS SERDESrx_intx_outBit SlipDeserializerrx_inclock / tx_inclockIOE supports SDR, DDR, or non-registered datapathIOE supports SDR, DDR,

The following tables list the number of true LVDS buffers supported in Cyclone V devices with theseconditions:• The LVDS channel count does not includ

RXTXSidePackageMember Code1915Top383-pin Micro FineLine BGAA587Right2116Bottom2020Top484-pin Ultra FineLine BGA 1212Right2424Bottom2828Top484-pin Fine

RXTXSidePackageMember Code2020Top484-pin Ultra FineLine BGAA91616Right2424Bottom2424Top484-pin FineLine BGA 88Right2424Bottom2828Top672-pin FineLine B

RXTXSidePackageMember Code156Top301-pin Micro FineLine BGAC587Right208Bottom1915Top383-pin Micro FineLine BGA 87Right2116Bottom2020Top484-pin Ultra Fi

RXTXSidePackageMember Code2020Top484-pin Ultra FineLine BGAC91616Right2424Bottom2424Top484-pin FineLine BGA 88Right2424Bottom2828Top672-pin FineLine B

Figure 1-5: ALM High-Level Block Diagram for Cyclone V Devicesdatacdataddatae1dataf1adder1datae0dataf0dataadatabcarry_incarry_outCombinational/Memory

RXTXSidePackageMember Code2020Top484-pin Micro FineLine BGAD71616Right2424Bottom2020Top484-pin Ultra FineLine BGA 1616Right2424Bottom2828Top484-pin Fi

Table 5-38: LVDS Channels Supported in Cyclone V SE Devices—PreliminaryRXTXSidePackageMember Code21Top484-pin Ultra FineLine BGAA2 and A444Right1210Bo

Related InformationGuideline: Use PLLs in Integer PLL Mode for LVDS on page 5-12Emulated LVDS Buffers in Cyclone V DevicesThe Cyclone V device family

Transmitter ClockingThe fractional PLL generates the parallel clocks (rx_outclock and tx_outclock), the load enable(LVDS_LOAD_EN) signal and the diffi

Figure 5-36: Serializer BypassThis figure shows the serializer bypass path. In DDR mode, tx_inclock clocks the IOE register. In SDRmode, data is passe

Figure 5-37: Receiver Block Diagramrx_inBit SlipDeserializerrx_inclock / tx_inclockIOE supports SDR, DDR, or non-registered datapathLVDS ReceiverFPGAF

Figure 5-39: Receiver Data Realignment RolloverThis figure shows a preset value of four bit-times before rollover occurs. The rx_cda_max signal pulses

You can select the rising edge option with the Quartus II MegaWizard Plug-In Manager. TheLVDS_diffioclk clock that is generated by the left and right

Figure 5-42: On-Chip Differential I/O TerminationDifferential Receiverwith On-Chip 100 ΩTerminationLVDSTransmitterZ0= 50 ΩZ0= 50 ΩRDTable 5-41: Quartu

Figure 5-43: Bit Orientation in the Quartus II SoftwareThis figure shows the data bit orientation of the x10 mode.9 8 7 6 5 4 3 2 1 010 LVDS BitsMSB L

Figure 1-6: ALM Connection Details for Cyclone V DevicesDQCLRDQCLRRow, ColumnDirect Link RoutingDQCLRLocalInterconnectLocalInterconnectDQCLRcarry_outG

Internal 8-Bit Parallel DataReceiver Channel Data NumberLSB PositionMSB Position3239540476485575663864719727910808711889512961031310411114112119151201

Figure 5-45: RSKM EquationConventions used for the equation:• RSKM—the timing margin between the receiver’s clock input and the data input sampling wi

For LVDS receivers, the Quartus II software provides an RSKM report showing the SW, TUI, and RSKMvalues for non-DPA LVDS mode:•You can generate the RS

ChangesVersionDate• Added the preliminary LVDS channels counts for Cyclone V SE, SX,and ST devices.• Updated the topic about LVDS input RDOCT to remov

ChangesVersionDate• Updated the tables listing the number of LVDS channels for theCyclone V devices:• Removed the F256 package from Cyclone V GX C3 de

ChangesVersionDate• Removed statements about LVDS SERDES being available on top andbottom banks only.• Removed the topic about LVDS direct loopback mo

6External Memory Interfaces in Cyclone V Devices2013.05.06CV-52006SubscribeSend FeedbackThe Cyclone V devices provide an efficient architecture that a

External Memory PerformanceTable 6-2: External Memory Interface Performance in Cyclone V DevicesThe maximum and minimum operating frequencies depend o

Guideline: Using DQ/DQS PinsThe following list provides guidelines on using the DQ/DQS pins:• The devices support DQ and DQS signals with DQ bus modes

Table 6-4: DQ/DQS Bus Mode Pins for Cyclone V DevicesMaximum Data Pins per GroupData Mask(Optional)DQSn SupportMode11YesYesx823YesYesx16DQ/DQS Groups

Normal ModeNormal mode allows two functions to be implemented in one Cyclone V ALM, or a single function of upto six inputs.Up to eight data inputs fr

x16x8SidePackageMember CodeTBDTBDTop383-pin Micro FineLine BGAA5TBDTBDLeftTBDTBDRightTBDTBDBottom15Top484-pin Ultra FineLine BGA 03Right16Bottom27Top4

x16x8SidePackageMember Code15Top484-pin Ultra FineLine BGAA904Right16Bottom15Top484-pin FineLine BGA 02Right16Bottom27Top672-pin FineLine BGA 06Right2

x16x8SidePackageMember CodeTBDTBDTop301-pin Micro FineLine BGAC4C5TBDTBDLeftTBDTBDRightTBDTBDBottomTBDTBDTop383-pin Micro FineLine BGATBDTBDLeftTBDTBD

x16x8SidePackageMember Code15Top484-pin Ultra FineLine BGAC904Right16Bottom15Top484-pin FineLine BGA 02Right16Bottom27Top672-pin FineLine BGA 06Right2

DQ/DQS Groups in Cyclone V GTTable 6-7: Number of DQ/DQS Groups Per Side in Cyclone V GT DevicesThis table lists the DQ/DQS groups for the soft memory

x16x8SidePackageMember Code15Top484-pin Micro FineLine BGAD704Right16Bottom15Top484-pin Ultra FineLine BGA 14Right16Bottom27Top484-pin FineLine BGA 02

DQ/DQS Groups in Cyclone V SXTable 6-8: Number of DQ/DQS Groups Per Side in Cyclone V SX DevicesThis table lists the DQ/DQS groups for the soft memory

The following device features are available for external memory interfaces:• DQS phase-shift circuitry• PHY Clock (PHYCLK) networks• DQS logic block•

Figure 6-1: External Memory Interface Datapath Overview for Cyclone V DevicesMemoryFPGADLL4nnn2nDQ (Read)DQ (Write)Read FIFODQS (Read)4n or 2n4DQS (Wr

Figure 6-2: DQS Pins and DLLs in Cyclone V E (A2 and A4) DevicesDLLReferenceClockΔtΔtΔtΔtDQS LogicBlocksDLLReferenceClockDLLtoIOEtoIOEtoIOEtoIOEDLLDQS

Figure 1-8: ALM in Arithmetic Mode for Cyclone V Devicesdatae0carry_incarry_outdataadatabdatacdataddatae1reg24-InputLUT4-InputLUT4-InputLUT4-InputLUTa

Figure 6-3: DQS Pins and DLLs in Cyclone V GX (C3) DevicesDQSPinDQSPinDQSPinDQSPinto IOEto IOEto IOEto IOEΔtΔtΔtΔtDLLReferenceClockΔtΔtΔtΔtDQS LogicBl

Figure 6-4: DQS Pins and DLLs in Cyclone V E (A5, A7, and A9), GX (C4, C5, C7, and C9), GT (D5, D7, andD9) DevicesDLLReferenceClockΔtΔtΔtΔtDQS LogicBl

Figure 6-6: DQS Pins and DLLs in Cyclone V SX (C2, C4, C5, and C6) and ST (D5 and D6) DevicesDQS LogicBlocksDLLReferenceClockDLLtoIOEtoIOEDLLDQSPinDQS

I/O banks between two DLLs have the flexibility to create multiple frequencies and multiple-type interfaces.These banks can use settings from either o

PLLDLLBottom RightBottom LeftTop RightTop Leftpllout———DLL_BRDLL Phase-ShiftThe DLL can shift the incoming DQS signals by 0° or 90°. The shifted DQS s

For the frequency range of each DLL frequency mode, refer to the device datasheet.Related InformationCyclone V Device DatasheetPHY Clock (PHYCLK) Netw

Figure 6-9: PHYCLK Networks in Cyclone V GX C3 DevicesLeftPLLRightPLLRightPLLSub-BankSub-BankI/O Bank 7Sub-BankSub-BankI/O Bank 8PHYCLK NetworksSub-Ba

Figure 6-12: PHYCLK Networks in Cyclone V SX C2, C4, C5, and C6 Devices, and Cyclone V ST D5 and D6DevicesLeftPLLSub-BankSub-BankI/O Bank 7Sub-BankSub

Update Enable CircuitryThe update enable circuitry enables the registers to allow enough time for the DQS delay settings to travelfrom the DQS phase-s

that any glitches on the DQS input signal during the end of a read operation and occurring while DQS is ina postamble state do not affect the DQ IOE r

Figure 1-9: ALM in Shared Arithmetic Mode for Cyclone V Devicesdatae0carry_inshared_arith_inshared_arith_outcarry_outdataadatabdatacdataddatae14-Input

Figure 6-16: Dynamic OCT Control Block for Cyclone V DevicesDFFDQDQDFFOCT ControlOCT ControlOCT Half-Rate Clock01DQDFFDQDFF10Write ClockOCT EnableOCT

Figure 6-17: IOE Input Registers for Cyclone V DevicesInput Reg AInput Reg BD QInput Reg CDouble Data Rate Input RegistersRead FIFOdatain [1]wrclkrdcl

Figure 6-18: IOE Output and Output-Enable Path Registers for Cyclone V DevicesThe following figure shows the registers available in the Cyclone V outp

Figure 6-19: Delay Chains in an I/O BlockD5 OCTdelaychainOCT EnableOutput EnableD5output-enabledelay chainD5 DelaydelaychainD1 Delaydelay chain01DQ or

Figure 6-21: Configuration Block (I/O and DQS)This figure shows the I/O configuration block and the DQS configuration block circuitry.datainbit0bit1bi

DescriptionFeature• DDR3—Burst length of 8 and burst chop of 4• DDR2—Burst lengths of 4 and 8• LPDDR2—Burst lengths of 2, 4, 8, and 16Memory Burst Len

DescriptionFeatureYou can select the region of memory to refresh during self-refresh through the moderegister to save power.Partial Array Self-Refresh

Numbers of MPFE Ports Per DeviceTable 6-14: Numbers of MPFE Command, Write-Data, and Read-Data Ports for Each Cyclone V DeviceMPFE PortsMember CodeVar

Figure 6-23: Hard Memory Controllers Bonding Support in Cyclone V E A7, A5, and A9 Devices, Cyclone VGX C4, C5, C7, and C9 Devices, and Cyclone V GT D

Figure 6-24: Hard Memory Controllers in Cyclone V SX C2, C4, C5, and C6 Devices, and Cyclone V ST D5 andD6 DevicesThis figure shows hard memory contro

ContentsLogic Array Blocks and Adaptive Logic Modules in Cyclone V Devices...1-1LAB ...

ChangesVersionDateReorganized content and updated template.2012.12.28December 2012Updated for the Quartus II software v12.0 release:• Restructured cha

Member CodePackage A9A7A5A4A2BottomTopBottomTopBottomTopBottomTopBottomTop242424402440024024F48440404040——————F67240404040——————F896Related Informatio

Hard Memory Controller Width for Cyclone V GTTable 6-17: Hard Memory Controller Width Per Side in Cyclone V GT Devices—PreliminaryMember CodePackage D

Document Revision HistoryChangesVersionDate• Moved all links to the Related Information section of respective topicsfor easy reference.• Added link to

ChangesVersionDate• Added the I/O and DQS configuration blocks topic.• Updated the term "Multiport logic" to "multi-port front end"

7Configuration, Design Security, and RemoteSystem Upgrades in Cyclone V Devices2013.06.11CV-52007SubscribeSend FeedbackThis chapter describes the conf

Table 7-1: Configuration Modes and Features Supported by Cyclone V DevicesRemote SystemUpdatePartialReconfigura-tion(14)DesignSecurityDecompres-sionMa

Table 7-2: MSEL Pin Settings for Each Configuration Scheme of Cyclone V DevicesValid MSEL[4..0]Power-On Reset(POR) DelayVCCPGM(V)Design SecurityFeatur

Figure 7-1: Configuration Sequence for Cyclone V DevicesPower supplies including VCCPDand VCCPGMreachrecommended operating voltagenSTATUS and nCONFIG

The operating voltage for the configuration input pin is independent of the I/O banks power supply, VCCIO,during configuration. Therefore, Cyclone V d

Related InformationCyclone V Device DatasheetProvides more information about tSTATUSand tCFGtiming parameters.InitializationThe initialization clock s

2Embedded Memory Blocks in Cyclone V Devices2013.05.06CV-52002SubscribeSend FeedbackThe embedded memory blocks in the devices are flexible and designe

Powered ByUser ModeInput/OutputConfigurationSchemeConfiguration PinVCCPD—InputJTAGTCKVCCPD—OutputJTAGTDOVCCPGM/VCCIO(15)I/OInputAllschemesCLKUSRPull-u

Powered ByUser ModeInput/OutputConfigurationSchemeConfiguration PinVCCPGM/VCCIO(15)I/OOutputFPP x16PR_READYVCCPGM/VCCIO(15)I/OOutputFPP x16PR_ERRORVCC

Fast Passive Parallel ConfigurationThe FPP configuration scheme uses an external host, such as a microprocessor, MAX®II device, or MAX Vdevice. This s

Pin Connections and GuidelinesObserve the following pin connections and guidelines for this configuration setup:• Tie the following pins of all device

When a device completes configuration, its nCEO pin is released low to activate the nCE pin of the nextdevice in the chain. Configuration automaticall

The maximum DCLK frequency supported by the AS configuration scheme is 100 MHz except for the ASmulti-device configuration scheme. You can source DCLK

Figure 7-6: Single Device AS x4 Mode ConfigurationAS_DATA0/ASDOAS_DATA1AS_DATA2AS_DATA3DCLKnCSOEPCQ Device FPGA Device10 kΩ10 kΩ10 kΩVCCPGMGNDnCEOnCEn

Using Multiple Configuration DataTo configure multiple Cyclone V devices in a chain using multiple configuration data, connect the devicesto an EPCS o

Using EPCS and EPCQ DevicesEPCS devices support AS x1 mode and EPCQ devices support AS x1 and AS x4 modes.Related Information• Serial Configuration (E

Related Information• AN 370: Using the Serial FlashLoader with the Quartus II Software• AN 418: SRunner: An Embedded Solution for Serial Configuration

Total RAM Bit (Kb)MLABM10KMemberCodeVariant RAM Bit (Kb)BlockRAM Bit (Kb)Block1,3491592551,190119C3Cyclone V GX2,7952954722,500250C44,8844246794,46044

Figure 7-9: Connection Setup for Programming the EPCQ Using the JTAG InterfaceDATA0DATA1DATA2DATA3DCLKnCSFPGA Device1 kΩGNDnCETCKTDOTMSTDIMSEL[4..0]nS

Figure 7-10: Connection Setup for Programming the EPCS Using the AS InterfaceDATADCLKnCSASDIAS_DATA1DCLKnCSOnCEnCONFIGnSTATUSnCEOCONF_DONEASDO10 kΩ10

Figure 7-11: Connection Setup for Programming the EPCQ Using the AS InterfaceUsing the AS header, the programmer serially transmits the operation comm

the byte sequence 02 1B EE 01 FA, the serial data transmitted to the device must be 0100-0000 1101-10000111-0111 1000-0000 0101-1111.You can use the P

Figure 7-13: Single Device PS Configuration Using an Altera Download CableDownload Cable10-Pin Male Header(PS Mode)VCCPGMVCCPGMVCCPGMVCCPGMVCCPGMVCCIO

Figure 7-14: Multiple Device PS Configuration when Both Devices Receive Different Sets of ConfigurationDataExternal Host(MAX II Device,MAX V Device, o

The nCE pins of the devices in the chain are connected to GND, allowing configuration for these devices tobegin and end at the same time.Using PC Host

• JTAG Secure Mode on page 7-34• AN 425: Using the Command-Line Jam STAPL Solution for Device Programming• Cyclone V Device DatasheetProvides more inf

Figure 7-17: JTAG Configuration of a Single Device Using a Download CableDownload Cable10-Pin Male Header(JTAG Mode) (Top View)FPGA DeviceDCLKnCONFIGC

JTAG Multi-Device ConfigurationYou can configure multiple devices in a JTAG chain.Pin Connections and GuidelinesObserve the following pin connections

Guideline: Implement External Conflict ResolutionIn the true dual-port RAM mode, you can perform two write operations to the same memory location.Howe

issue all JTAG instructions. Otherwise, you can only issue the BYPASS, IDCODE, and SAMPLE JTAGinstructions.You can use the CONFIO_IO JTAG instruction

Figure 7-20: Compressed and Uncompressed Serial Configuration Data in the Same Configuration FilenCEGNDnCEOFPGADevice 1FPGADevice 2nCE nCEO N.C.Serial

Configuration ImagesEach Cyclone V device in your system requires one factory image. The factory image is a user-definedconfiguration image that conta

Remote System Upgrade CircuitryThe remote system upgrade circuitry contains the remote system upgrade registers, watchdog timer, and astate machine th

Related InformationRemote System Upgrade (ALTREMOTE_UPDATE) Megafunction User GuideRemote System Upgrade RegistersTable 7-6: Remote System Upgrade Reg

Control RegisterTable 7-7: Control Register BitsDescriptionResetValue(16)NameBitApplication not Factory bit. Indicates theconfiguration image type cur

1. After power-up, the remote system upgrade registers are reset to 0 and the factory configuration imageis loaded.2.The user logic sets the AnF bit t

• Security against copying—the security key is securely stored in the Cyclone V device and cannot be readout through any interface. In addition, as co

Security Key TypesCyclone V devices offer two types of keys—volatile and non-volatile. The following table lists the differencesbetween the volatile k

Security LevelDevice AcceptsEncrypted FileDevice AcceptsUnencrypted FileTamper ProtectionBit SettingSecurity ModeSecure with tamperresistantYesNoSetVo

Figure 2-2: Same-Port Read-During-Write: New Data ModeThis figure shows sample functional waveforms of same-port read-during-write behavior in the “ne

Document Revision HistoryChangesVersionDateUpdated the Configuration Error Handling section.2013.06.11June 2013Removed support for active serial multi

8SEU Mitigation for Cyclone V Devices2013.11.12CV-52008SubscribeSend FeedbackThis chapter describes the error detection features in Cyclone V devices.

applications that require the device to operate error-free may require that your designs account for theseerrors.You can enable the error detection ci

Timing Interval (µs)Member CodeVariant1.79D5Cyclone V GT 2.33D73.23D91.77A2Cyclone V SE1.77A42.31A52.31A61.77C4Cyclone V SX 2.31C52.31C62.31D5Cyclone

Table 8-3: CRC Calculation Time in Cyclone V DevicesThe following table lists the minimum and maximum time taken to calculate the CRC value:• The mini

3. In the Category list, click Error Detection CRC.4. Turn on Enable Error Detection CRC_ERROR pin.5.To set the CRC_ERROR pin as output open drain, tu

Table 8-5: Error Detection RegistersDescriptionWidth (Bits)NameContains the 32-bit CRC signature calculated for the currentframe. If the CRC value is

Table 8-6: Error Type in EMRThe following table lists the possible error types reported in the error type field in the EMR.DescriptionError TypeBit 0B

comes last. Therefore, you can start retrieving the contents of the EMR at the rising edge of the CRC_ERRORpin. The pin stays high until the current f

Table 8-8: EDERROR_INJECT instructionDescriptionInstruction CodeJTAG InstructionUse this instruction to inject errors into theconfiguration data. This

DescriptionMemory TypeOutput ModeThe RAM outputs “don’t care” or “unknown” value. TheQuartus II software analyzes the timing between write andread ope

9JTAG Boundary-Scan Testing in Cyclone V Devices2013.05.06CV-52009SubscribeSend FeedbackThis chapter describes the boundary-scan test (BST) features i

Table 9-1: IDCODE Information for Cyclone V DevicesIDCODE (32 Bits)Member CodeVariantLSB (1 Bit)ManufactureIdentity(11 Bits)Part Number(16 Bits)Versio

IDCODE (32 Bits)Member CodeVariantLSB (1 Bit)ManufactureIdentity(11 Bits)Part Number(16 Bits)Version (4 Bits)1000 0110 11100010 1101 000100010000C2Cyc

DescriptionInstruction CodeJTAG InstructionPlaces the 1-bit bypass register betweenthe TDI and TDO pins. During normaldevice operation, the 1-bit bypa

DescriptionInstruction CodeJTAG Instruction• Places the 1-bit bypass registerbetween the TDI and TDO pins.During normal operation, the 1-bitbypass reg

If the device is in a reset state and the nCONFIG or nSTATUS signal is low, the device IDCODEmight not be read correctly. To read the device IDCODE co

Table 9-3: Supported TDO and TDI Voltage CombinationsThe TDO output buffer for VCCPDof 3.3 V or 3.0 V meets VOH(MIN) of 2.4 V, and the TDO output buff

Enabling and Disabling IEEE Std. 1149.1 BST CircuitryThe IEEE Std. 1149.1 BST circuitry is enabled after the Cyclone V device powers up. However for C

IEEE Std. 1149.1 Boundary-Scan RegisterThe boundary-scan register is a large serial shift register that uses the TDI pin as an input and the TDO pinas

Figure 9-2: User I/O BSC with IEEE Std. 1149.1 BST Circuitry for Cyclone V Devices01OUTPUTOEINPUTINPUTOUTPUTOEFrom orTo DeviceI/O CellCircuitryAnd/OrL

Figure 2-5: Mixed-Port Read-During-Write: Don’t Care or Constrained Don’t Care ModeThis figure shows a sample functional waveform of mixed-port read-d

CommentsDrivesCapturesPin TypeInputUpdateRegisterOE UpdateRegisterOutputUpdateRegisterInputCaptureRegisterOE CaptureRegisterOutputCaptureRegisterPIN_I

10Power Management in Cyclone V Devices2013.06.28CV-52010SubscribeSend FeedbackThis chapter describes the hot-socketing feature, power-on reset (POR)

The equation shows that power is design-dependent and is determined by the operating frequency of yourdesign. Cyclone V devices minimize static and dy

Hot-socketing circuitry prevents excess I/O leakage during power up. When the voltage ramps up veryslowly, I/O leakage is still relatively low, even a

Figure 10-3: Power-Up Sequence Recommendation for Cyclone V DevicesPower up VCCBATat any time. Ramp up the power rails in each group to a minimum of 8

For details about the minimum current requirements, refer to the PowerPlay Early Power Estimator (EPE),and compare to the information listed in Table

The POR circuitry checks the functionality of the I/O level shifters powered by the VCCPDand VCCPGMpower supplies during power-up mode. The main POR c

Document Revision HistoryChangesVersionDate• Added power-up sequences for Cyclone V SX, SE and ST devices.• Added the current transient that occurs on

Related Information• Internal Memory (RAM and ROM) User GuideProvides more information about .mif files.• Quartus II HandbookProvides more information

MLABM10KFeatures• Registered outputports—Cleared.• Unregistered output ports—Readmemory contents.Output ports arecleared.Power-up stateOutput register

Mixed-Width Port ConfigurationsThe mixed-width port configuration is supported in the simple dual-port RAM and true dual-port RAMmemory modes.MLABs do

Byte Enable in Embedded Memory Blocks...2-13Byte Enable Contr

Port APort B512 x 20512 x 161K x 101K x 82K x 52K x 44K x 28K x 1Yes—Yes—Yes———512 x 20Embedded Memory ModesTo avoid corrupting the memory contents, d

DescriptionMLABSupportM10KSupportMemory ModeYou can use the memory blocks as ROM.• Initialize the ROM contents of the memory blocks using a .mifor .he

Memory ModeClocking ModeFIFOROMTrue Dual-PortSimple Dual-PortSingle-Port—YesYesYesYesInput/output clock mode—YesYes——Independent clock modeThe clock e

Independent Clock Enables in Clocking ModesIndependent clock enables are supported in the following clocking modes:• Read/write clock mode—supported f

Data Bits Writtenbyteena[1:0][9:0]—01Table 2-13: byteena Controls in x40 Data WidthData Bits Writtenbyteena[3:0][9:0][19:10][29:20][39:30]1111 (defaul

Memory Blocks Packed Mode SupportThe M10K memory blocks support packed mode.The packed mode feature packs two independent single-port RAM blocks into

Figure 2-9: Address Clock Enable During the Write Cycle WaveformThis figure shows the address clock enable waveform during the write cycle.inclockwren

ChangesVersionDate• Reorganized content and updated template.• Added memory capacity information from the Cyclone V DeviceOverview for easy reference.

3Variable Precision DSP Blocks in Cyclone V Devices2013.05.06CV-52003SubscribeSend FeedbackThis chapter describes how the variable-precision digital s

Supported Operational Modes in Cyclone V DevicesTable 3-1: Variable Precision DSP Blocks Operational Modes for Cyclone V DevicesChainout SupportInputC

Types of Clock Networks...4-3Clock Source

ResourcesTable 3-2: Number of Multipliers in Cyclone V DevicesThe table lists the variable-precision DSP resources by bit precision for each Cyclone V

Design ConsiderationsYou should consider the following elements in your design:• Operational modes• Internal coefficient and pre-adder• Accumulator• C

Block ArchitectureThe Cyclone V variable precision DSP block consists of the following elements:• Input register bank• Pre-adder• Internal coefficient

Input Register BankThe input register bank consists of data, dynamic control signals, and two sets of delay registers.All the registers in the DSP blo

Figure 3-2: Input Register of a Variable Precision DSP Block in 18 x 19 Mode for Cyclone V DevicesThe figures show the data registers only. Registers

Figure 3-3: Input Register of a Variable Precision DSP Block in 27 x 27 Mode for Cyclone V DevicesThe figures show the data registers only. Registers

There are two multipliers per variable precision DSP block. You can configure these two multipliers inseveral operational modes:• One 27 x 27 multipli

ACCUMULATELOADCONSTNEGATEDescriptionFunction1X0Adds the currentresult to the previousaccumulate result.Accumulation1X1This function takesthe current r

Operational Mode DescriptionsThis section describes how you can configure an Cyclone V variable precision DSP block to efficientlysupport the followin

18 x 18 or 18 x 19 Independent MultiplierFigure 3-5: Two 18 x 18 or 18 x 19 Independent Multiplier Mode per Variable Precision DSP Block forCyclone V

Guideline: Adhere to the LVDS I/O Restrictions and Differential Pad PlacementRules...

20 x 24 Independent MultiplierFigure 3-7: One 20 x 24 Independent Multiplier Mode per Variable Precision DSP Block for Cyclone V DevicesIn this mode,

18 x 19 Complex MultiplierFigure 3-10: One 18 x 19 Complex Multiplier with Two Variable Precision DSP Blocks for Cyclone V DevicesVariable-Precision D

Multiplier Adder Sum ModeFigure 3-11: One Sum of Two 18 x 19 Multipliers with One Variable Precision DSP Block for Cyclone VDevicesInput Register Bank

Systolic FIR ModeThe basic structure of a FIR filter consists of a series of multiplications followed by an addition.Figure 3-13: Basic FIR Filter Equ

Figure 3-15: 18-Bit Systolic FIR Mode for Cyclone V DevicesInput Register Bankdataa_y0[17..0]dataa_z0[17..0]dataa_x0[17..0]COEFSELA[2..0]datab_y1[17..

Figure 3-16: 27-Bit Systolic FIR Mode for Cyclone V DevicesInput Register Bankdataa_y0[25..0]dataa_z0[25..0]dataa_x0[26..0]COEFSELA[2..0]Pre-Adder+/-I

ChangesVersionDateInitial release.1.0May 2011Altera CorporationVariable Precision DSP Blocks in Cyclone V DevicesSend Feedback3-19Document Revision Hi

4Clock Networks and PLLs in Cyclone V Devices2013.05.06CV-52004SubscribeSend FeedbackThis chapter describes the advanced features of hierarchical cloc

Table 4-1: Clock Resources in Cyclone V Devices—PreliminarySource of Clock ResourceNumber of ResourcesAvailableDeviceClock ResourceCLK[0..11][p,n] pin

Source of Clock ResourceNumber of ResourcesAvailableDeviceClock Resource—Cyclone V E A2 and A4PCLK networksPLD-transceiver interface clocks,I/O pins,

Transmitter Blocks...5-62Seriali

Figure 4-1: GCLK Networks in Cyclone V DevicesThis figure represents the top view of the silicon die that corresponds to a reverse view of the device

Periphery Clock NetworksCyclone V devices provide only horizontal PCLKs from the left periphery.Clock outputs from the programmable logic device (PLD)

Figure 4-4: Hierarchical Clock Networks in Each Spine Clock Per QuadrantSCLKColumn I/O clock: clock that drivesthe I/O column core registersand I/O in

Figure 4-5: Dual-Regional Clock Region for Cyclone V DevicesThis figure represents the top view of the silicon die that corresponds to a reverse view

Related Information• PLLs and Clocking on page 5-12Provides more information about HSSI outputs.• LVDS Interface with External PLL Mode on page 5-15Pr

CLK (p/n Pins)Clock ResourcesCLK[6]RCLK[52,53,54,55,56,57,72,78]CLK[7](3)RCLK[52,53,54,55,56,57,73,79]CLK[8]RCLK[0,4,8,10,14,18,40,41,42,43,44,45,64,6

Pin Mapping in Cyclone V DevicesTable 4-6: Mapping Between the Input Clock Pins, PLL Counter Outputs, and Clock Control Block InputsFed byClockAny of

Figure 4-7: RCLK Control Block for Cyclone V DevicesCLKpPinPLL CounterOutputsInternal LogicCLKnPinEnable/DisableRCLKInternalLogicStatic Clock Select2W

Figure 4-9: External PLL Output Clock Control Block for Cyclone V DevicesPLL CounterOutputsFPLL_<#>_CLKOUT pinIOEInternalLogic9Enable/DisableSta

Figure 4-10: clkena Implementation with Clock Enable and Disable CircuitThis figure shows the implementation of the clock enable and disable circuit o

Bonding Support...6-32Hard Me

Cyclone V PLLsPLLs provide robust clock management and synthesis for device clock management, external system clockmanagement, and high-speed I/O inte

PLL Physical Counters in Cyclone V DevicesThe physical counters for the fractional PLLs are arranged in the following sequences:• Up-to-down• Down-to-

Figure 4-14: PLL Locations for Cyclone V GX C3 DeviceThis figure represents the top view of the silicon die that corresponds to a reverse view of the

Figure 4-16: PLL Locations for Cyclone V E A7 Device, Cyclone V GX C7 Device, Cyclone V GT D7 Device,Cyclone V SE A5 and A6 Devices, Cyclone V SX C5 a

Figure 4-17: PLL Locations for Cyclone V E A9 Device, Cyclone V GX C9 Device, and Cyclone V GT D9 DeviceThis figure represents the top view of the sil

Fractional PLL UsageYou can configure the fractional PLL to function either in the integer or in the enhanced fractional mode.One fractional PLL can u

Figure 4-19: Dual-Purpose Clock I/O Pins Associated with PLL for Cyclone V DevicesC0C1C2C3C4C5C6C7C8MI/O / FPLL_<#>_CLKOUT0/ FPLL_<#>_CLKO

When areset is driven high, the PLL counters reset, clearing the PLL output and placing the PLL out-of-lock. The VCO is then set back to its nominal s

Source Synchronous ModeIf the data and clock arrive at the same time on the input pins, the same phase relationship is maintained atthe clock and data

Figure 4-21: Example of Phase Relationship Between the Clock and Data in LVDS Compensation ModeData PinData at the RegisterClock at the RegisterPLL Re

JTAG Single-Device Configuration...7-24JTAG Multi-Device Con

Figure 4-23: Example of Phase Relationship Between the PLL Clocks in Normal ModePLL Clock at theRegister Clock PortDedicated PLLClock OutputsPhase Ali

Figure 4-24: ZDB Mode in Cyclone V PLLsinclk÷N PFDVCOCP/LFC0C1C2C3C4C5C6C7C8MEXTCLKOUT[1]EXTCLKOUT[0]fboutfbin210FPLL_<#>_FBMultiplexerFigure 4-

One of the dual-purpose external clock outputs becomes the fbin input pin in this mode. The externalfeedback input pin, fbin is phase-aligned with the

Related InformationPLL External Clock I/O Pins on page 4-19Provides more information about PLL clock outputs.Clock Multiplication and DivisionEach Cyc

Related InformationAltera Phase-Locked Loop (ALTERA_PLL) Megafunction User GuideProvides more information about PLL software support in the Quartus II

Figure 4-28: Automatic Clock Switchover Circuit Block DiagramThis figure shows a block diagram of the automatic switchover circuit built into the PLL.

period difference is within 20%, the clock sense block detects when a clock stops toggling. However, the PLLmay lose lock after the switchover is comp

Figure 4-30: Clock Switchover Using the clkswitch (Manual) ControlThis figure shows a clock switchover waveform controlled by the clkswitch signal. In

Figure 4-31: Manual Clock Switchover Circuitry in Cyclone V PLLsClock SwitchControl LogicN CounterPFDinclk0inclk1muxout refclkfbclkclkswitchYou can de

Figure 4-32: VCO Switchover Operating Frequency∆FvcoPrimary Clock Stops RunningVCO Tracks Secondary ClockSwitchover OccursPLL Reconfiguration and Dyna

JTAG Boundary-Scan Testing in Cyclone V Devices...9-1BST Operation Control ...

ChangesVersionDate• Added note to indicate that the figures shown are the top view of thesilicon die.• Removed DPA support.• Updated clock resources t

5I/O Features in Cyclone V Devices2013.06.21CV-52005SubscribeSend FeedbackThis chapter provides details about the features of the Cyclone V I/O elemen

Table 5-1: Package Plan for Cyclone V E Devices—PreliminaryF896F672F484U484F256U324M484M383Member CodeGPIOGPIOGPIOGPIOGPIOGPIOGPIOGPIO——224224128176—2

Table 5-5: Package Plan for Cyclone V SX Devices—PreliminaryF896U672Member CodeXCVRHPS I/OFPGA GPIOXCVRHPS I/OFPGA GPIO———6181145C2———6181145C49181288

I/O Vertical Migration for Cyclone V DevicesFigure 5-1: Vertical Migration Capability Across Cyclone V Device Packages and Densities—PreliminaryThe ar

Verifying Pin Migration CompatibilityYou can use the Pin Migration View window in the Quartus II software Pin Planner to assist you in verifyingwhethe

Standard SupportI/O StandardJESD8-B3.0 V LVTTL/3.0 V LVCMOSPCI Rev. 2.23.0 V PCI(6)PCI-X Rev. 1.03.0 V PCI-X(7)JESD8-52.5 V LVCMOSJESD8-71.8 V LVCMOSJ

Standard SupportI/O StandardANSI/TIA/EIA-644LVDS—RSDS(8)—Mini-LVDS(9)—LVPECLJESD8-13SLVS—Sub-LVDS—HiSpiJESD79-3DSSTL-15—SSTL-135—SSTL-125—HSUL-12JESD7

HPS Row I/OHPS Column I/OStandard SupportI/O StandardYes——SSTL-135Yes——SSTL-125Yes——HSUL-12I/O Standards Voltage Levels in Cyclone V DevicesTable 5-9:

VTT(V)(Board TerminationVoltage)VREF(V)(Input RefVoltage)VCCPD(V)(Pre-DriverVoltage)VCCIO(V)I/O StandardOutputInput(10)1.25—2.52.5VCCPDDifferential SS