Altera Stratix V Avalon-ST Uživatelský manuál stáhnout pdf (Strana 28)

Table 3-1: Parameters to Specify on the Generation Tab in Qsys

Parameter Value

Create testbench Qsys system Standard, BFMs for standard Avalon interfaces

Create simulation model Verilog

Allow mixed-language simulation Turn this option off

Output Directory

Path <working_dir>/top

Testbench <working_dir>/top/testbench

1. Click Generate to generate the simulation and testbench files.

2. On the File menu, click Save.

Generating Quartus II Synthesis Files

1. On the Generate menu, select Generate HDL.

2. For Create HDL design files for synthesis, select Verilog.

You can leave the default settings for all other items.

3. Click Generate to generate files for Quartus II synthesis.

4. Click Finish when the generation completes.

Understanding the Generated Files

Table 3-2: Qsys Generation Output Files

Directory Description

<testbench_dir>/<variant_name>/synthesis Includes the top-level HDL file for the Hard IP for

PCI Express and the .qip file that lists all of the

necessary assignments and information required to

process the IP core in the Quartus II compiler.

Generally, a single .qip file is generated for each IP

core. These files are used for Quartus II synthesis.

<testbench_dir>/<variant_name>/synthesis/submodules

Includes the HDL files necessary for Quartus II

synthesis.

<testbench_dir>/<variant_name>/testbench/<cad_

vendor>

Includes the HDL source files and scripts for the

simulation testbench.

3-4

Generating Quartus II Synthesis Files

UG-01097_avst

2014.08.18

Altera Corporation

Getting Started with the Configuration Space Bypass Mode Qsys Example Design

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Altera Stratix V Avalon-ST Uživatelský manuál Strana 28