Altera Stratix V Avalon-ST Uživatelský manuál Strana 274
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- Tabulka s obsahem
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Hodnocené. / 5. Na základě hodnocení zákazníků
Table 18-2: Link Hangs in L0
Possible Causes Symptoms and Root Causes Workarounds and Solutions
Avalon-ST signaling
violates Avalon-ST
protocol
Avalon-ST protocol violations
include the following errors:
• More than one tx_st_sop
per tx_st_eop.
• Two or more tx_st_eop’s
without a corresponding tx_
st_sop.
• rx_st_valid is not asserted
with tx_st_sop or tx_st_
eop.
These errors are applicable to
both simulation and hardware.
Add logic to detect situations where tx_st_
ready remains deasserted for more than 100
cycles. Set post-triggering conditions to check
for the Avalon-ST signalling of last two TLPs to
verify correct tx_st_sop and tx_st_eop
signalling.
Incorrect payload
size
Determine if the length field of
the last TLP transmitted by End
Point is greater than the InitFC
credit advertised by the link
partner. For simulation, refer to
the log file and simulation
dump. For hardware, use a
third-party logic analyzer trace
to capture PCIe transactions.
If the payload is greater than the initFC credit
advertised, you must either increase the InitFC
of the posted request to be greater than the max
payload size or reduce the payload size of the
requested TLP to be less than the InitFC value.
Flow control credit
overflows
Determine if the credit field
associated with the current TLP
type in the tx_cred bus is less
than the requested credit value.
When insufficient credits are
available, the core waits for the
link partner to release the
correct credit type. Sufficient
credits may be unavailable if the
link partner increments credits
more than expected, creating a
situation where the Stratix V
Hard IP for PCI Express IP Core
credit calculation is out-of-sink
with its link partner.
Add logic to detect conditions where the tx_st_
ready signal remains deasserted for more than
100 cycles. Set post-triggering conditions to
check the value of the tx_cred* and tx_st_*
interfaces. Add a FIFO status signal to
determine if the TXFIFO is full.
UG-01097_avst
2014.12.15
Debugging Link Failure in L0 Due To Deassertion of tx_st_ready
18-5
Debugging
Altera Corporation
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- User Guide 1
- Datasheet 2
- Features 3
- Interface 4
- Release Information 7
- Device Family Support 7
- UG-01097_avst 10
- 2014.12.15 10
- Debug Features 11
- IP Core Verification 11
- Recommended Speed Grades 12
- • All Development Kits 14
- PCI Express 15
- Qsys Design Flow 16
- Generating the Testbench 17
- Simulating the Example Design 18
- Directory Description 19
- Time TLP Type Payload 19
- TLP Header 19
- Modifying the Example Design 23
- Separate Component 24
- Generating the Qsys System 27
- Parameter Value 28
- Parameter Settings 38
- Parameter Value Description 39
- Device Capabilities 45
- Error Reporting 47
- Link Capabilities 48
- MSI and MSI-X Capabilities 49
- Slot Capabilities 50
- Power Management 51
- PHY Characteristics 52
- Avalon‑ST RX Interface 54
- Packet TLP 59
- Aligned Addresses 64
- Single Packet Per Cycle 67
- Avalon-ST TX Interface 70
- Data 0 Header 2 83
- Clock Signals 85
- ECRC Forwarding 90
- Error Signals 90
- Interrupts for Endpoints 91
- Completion Side Band Signals 93
- Signal Directi 94
- Description 94
- Related Information 101
- Parity Signals 102
- LMI Signals 103
- Signal Direction Description 104
- Altera Corporation 107
- Send Feedback 107
- Field and Bit Map 112
- 0134678951 112
- Bit(s) Field Description 113
- Power Management Signals 115
- 15 011623 8 2791213142431 117
- Transceiver Reconfiguration 118
- Serial Data Signals 119
- PIPE Interface Signals 123
- Test Signals 128
- Registers 129
- Altera-Defined VSEC Registers 137
- CvP Registers 138
- 2014.08.18 139
- Bits Register Description 142
- Reset and Clocks 145
- Example Design 146
- Hard IP for PCI Express 146
- Clock Domains 149
- Data Rate Frequency 150
- Clock Summary 152
- Interrupts 153
- MSI Interrupts 154
- Allocated 155
- Implementing MSI-X Interrupts 156
- Legacy Interrupts 158
- Interrupts for Root Ports 159
- Error Handling 160
- Physical Layer Errors 161
- Data Link Layer Errors 161
- Transaction Layer Errors 162
- Error Type Description 163
- Status Bit Conditions 166
- IP Core Architecture 168
- Hard IP for PCI Express 169
- Top-Level Interfaces 170
- Avalon-ST Interface 170
- Clocks and Reset 171
- Hard IP Reconfiguration 171
- Transaction Layer 172
- Configuration Space 173
- (Soft Logic) 175
- Altera FPGA 175
- Protocol Extensions Supported 179
- Data Link Layer 179
- Physical Layer 181
- TX Packets 182
- Supported Message Types 184
- INTX Messages 184
- Power Management Messages 185
- Error Signaling Messages 186
- Locked Transaction Message 187
- Slot Power Limit Message 187
- Vendor-Defined Messages 187
- Hot Plug Messages 188
- Receive Buffer Reordering 190
- Using Relaxed Ordering 192
- Throughput Optimization 195
- Throughput of Posted Writes 197
- Design Implementation 199
- CONF_DONE 200
- Endpoint Reset 200
- Root Port Reset 200
- SDC Timing Constraints 201
- Optional Features 203
- ECRC on the RX Path 204
- ECRC on the TX Path 205
- Subscribe 208
- Testbench and Design Example 212
- Root Port Testbench 215
- Chaining DMA Design Examples 215
- Root Complex 217
- Chaining DMA 217
- Hard IP for 217
- BAR/Address Map 220
- Memory BAR Mapping 221
- Bit Field Description 222
- Addr Register Name 222
- Offset to Base 225
- Descriptor Type Description 225
- Byte Address 225
- Bits[21:18] Bit[17] Bit[16] 226
- Descriptor Field Endpoint 226
- RC Access Description 226
- Test Driver Module 227
- DMA Write Cycles 228
- Shared Memory 229
- DMA Read Cycles 230
- Registers (BAR2) 231
- Root Port Design Example 232
- Root Port 233
- Variation 233
- (variation_name.v) 233
- Root Port BFM 234
- BFM Configuration Procedures 235
- BFM Request Interface 235
- BFM Memory Map 236
- Offset (Bytes) Description 238
- BFM Procedures and Functions 242
- Location altpcietb_bfm_rdwr.v 243
- Express address 244
- Shared Memory Constants 251
- Constant Description 252
- Location 257
- Debugging Simulations 269
- Debugging 270
- Setting Up Simulation 276
- Use Third-Party PCIe Analyzer 277
- BIOS Enumeration Issues 277
- Address[31:2] 278
- Figure A-6: I/O Read Request 280
- 7 6 5 4 3 2 1 0 284
- Core Config 8 4 1 284
- Additional Information 286
- Date Version Changes Made 287
- How to Contact Altera 290
- Typographic Conventions 291
- Visual Cue Meaning 292
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