Altera Stratix V Advanced Systems Development Board Uživatelský manuál stáhnout pdf (Strana 61)

Chapter 2: Board Components 2–51

Memory

January 2014 Altera Corporation Stratix V Advanced Systems Development Board

Reference Manual

CASN

1.5-V SSTL Class I AK33 K17 Column address strobe

CKE

1.5-V SSTL Class I AE31 K18 Clock enable

CLK_N

Differential 1.5-V

SSTL Class I

AE32 P18 Differential output clock

CLK_P

Differential 1.5-V

SSTL Class I

AD32 P19 Differential output clock

CSN

1.5-V SSTL Class I AG33 L17 Chip select

DM0

1.5-V SSTL Class I BA30 E21 Data write mask

DM1

1.5-V SSTL Class I AG25 K22 Data write mask

DM2

1.5-V SSTL Class I AN30 R21 Data write mask

DM3

1.5-V SSTL Class I AJ28 T18 Data write mask

DM4

1.5-V SSTL Class I AP27 H13 Data write mask

DM5

1.5-V SSTL Class I AR29 M15 Data write mask

DM6

1.5-V SSTL Class I AT27 U15 Data write mask

DM7

1.5-V SSTL Class I BA28 A14 Data write mask

DQ0

1.5-V SSTL Class I AY31 E20 Data bus

DQ1

1.5-V SSTL Class I BC32 B20 Data bus

DQ2

1.5-V SSTL Class I BB32 F22 Data bus

DQ3

1.5-V SSTL Class I AW30 F21 Data bus

DQ4

1.5-V SSTL Class I BD32 A22 Data bus

DQ5

1.5-V SSTL Class I BD31 A20 Data bus

DQ6

1.5-V SSTL Class I BB30 B22 Data bus

DQ7

1.5-V SSTL Class I BC31 C21 Data bus

DQ8

1.5-V SSTL Class I AF29 G22 Data bus

DQ9

1.5-V SSTL Class I AF28 J21 Data bus

DQ10

1.5-V SSTL Class I AG29 F20 Data bus

DQ11

1.5-V SSTL Class I AG26 K21 Data bus

DQ12

1.5-V SSTL Class I AG30 J22 Data bus

DQ13

1.5-V SSTL Class I AG27 L21 Data bus

DQ14

1.5-V SSTL Class I AK29 G20 Data bus

DQ15

1.5-V SSTL Class I AG28 K20 Data bus

DQ16

1.5-V SSTL Class I AT30 R22 Data bus

DQ17

1.5-V SSTL Class I AR30 P21 Data bus

DQ18

1.5-V SSTL Class I AP30 T22 Data bus

DQ19

1.5-V SSTL Class I AU32 M22 Data bus

DQ20

1.5-V SSTL Class I AJ31 U20 Data bus

DQ21

1.5-V SSTL Class I AH30 V19 Data bus

DQ22

1.5-V SSTL Class I AJ30 T21 Data bus

DQ23

1.5-V SSTL Class I AH31 U21 Data bus

Table 2–24. FPGA2 DDR3 Devices Pin Assignments, Schematic Signal Names, and Functions (Part 4 of 6)

Board

Reference

Schematic

Signal Name

I/O Standard Stratix V GX FPGA2 Device Pin Number Description

1 2 ... 56 57 58 59 60 61 62 63 64 65 66 ... 83 84

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