Altera Stratix IV GX FPGA Development Board Uživatelský manuál stáhnout pdf (Strana 55)

Chapter 2: Board Components 2–47

Memory

August 2012 Altera Corporation Stratix IV GX FPGA Development Board

Reference Manual

Figure 2–14 shows the SDI cable equalizer.

Memory

This section describes the board’s memory interface support, signal names, types, and

connectivity relative to the Stratix IV GX device. The board has the following memory

interfaces:

■ DDR3 bottom port

■ DDR3 top port

■ QDRII+ top port 0

■ QDRII+ top port 1

■ SSRAM

■ Flash

f For more information about the memory interfaces, refer to the External Memory

Interface Handbook.

U2.7 Bypass enable

SDI_RX_BYPASS

2.5-V T4 —

U2.14 Device enable

SDI_RX_EN

2.5-V M6

—

(Automatically driven

by carrier detect)

Table 2–45. SDI Video Input Interface Pin Assignments, Schematic Signal Names, and Functions (Part 2 of 2)

Board

Reference

Description

Schematic

Signal Name

I/O Standard

MAX II CPLD EPM2210

System Controller

Pin Number

Stratix IV GX Device

Pin Number

Figure 2–14. SDI Cable Equalizer

BYPASS

MUTE

REF

1.0 μF

75 Ω

37.4 Ω

1.0 μF

SDI

SDO

MUTE

REF

BYPASS

AEC+

AEC–

75 Ω

MUTE

Coaxial Cable

LMH0344 3G SDI

Adaptive Cable

Equalizer

To FPGA

3.9 nH

1 2 ... 50 51 52 53 54 55 56 57 58 59 60 ... 81 82

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