Altera Stratix IV GX FPGA Development Board Uživatelský manuál stáhnout pdf (Strana 31)

Chapter 2: Board Components 2–23

Clock Circuitry

August 2012 Altera Corporation Stratix IV GX FPGA Development Board

Reference Manual

Table 2–20 lists the external clock inputs for the Stratix IV GX FPGA development

board.

Figure 2–7. Stratix IV GX FPGA Development Board Transceiver Reference Clock Inputs

B1B2

B6B5

QL0 QL1 QL2

REFCLK_L0p

REFCLK_L1p

PCIE_REFCLK_P

REFCLK_L2p

REFCLK_L3p

REFCLK_L4p

REFCLK_L5p

CLK_155_P

CLKINLT_100_P

LVDS, OCT 100 Ω

LVPECL, OCT 100 Ω

HCSL, NO OCT

CLK_125_P

CLKINRT_100_P

LVDS, OCT 100 Ω

CLK_156_P

LVDS, OCT 100 Ω

CLK_148_P

LVDS, OCT 100 Ω

QR0 QR1 QR2

REFCLK_R0p

REFCLK_R1p

REFCLK_R2p

REFCLK_R3p

REFCLK_R4p

REFCLK_R5p

PCIe Edge

Connector

REFCLK INPUT

SMA SMA

LVPECL or

Single-Ended

2-to-4 buffer

100 M*

CLK_SEL

CLKINTOP_100_P

CLKINBOT_100_P

CLKINRT_100_P

CLKINLT_100_P

DIPSW

SW4-5

To GPLL Clock Inputs

Right Edge

REFCLK Inputs

Left Edge

REFCLK Inputs

*The 100 MHz oscillator (X6) can be programmed

to any frequency between 10 MHz and 800 MHz

but powers up to 100 MHz using the clock control

GUI installed with the kit CD.

Table 2–20. Stratix IV GX FPGA Development Board Clock Inputs (Part 1 of 2)

Source Schematic Signal Name Pin I/O Standard Description

CLK_125_P0 J2 LVDS

125 MHz oscillator which drives the

transceiver reference clock input with 100 Ω

on-chip termination (OCT).

CLK_125_P1 AF34 LVDS

125 MHz oscillator which drives the global

clock input with parallel OCT.

X2 CLK_156_P AA2 LVDS

156.25 MHz oscillator which drives the

transceiver reference clock input with 100 Ω

OCT.

X3 CLK_148_P AL2 LVDS

148.5 MHz oscillator which drives the

transceiver reference clock input with 100 Ω

OCT.

1 2 ... 26 27 28 29 30 31 32 33 34 35 36 ... 81 82

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