Altera RapidIO MegaCore Function manuály

Uživatelské manuály a uživatelské příručky pro Měřící nástroje Altera RapidIO MegaCore Function.
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Altera RapidIO MegaCore Function Uživatelský manuál (198 strany)

Značka: Altera | Kategorie: Měřící nástroje | Velikost: 3.50 MB |

Tabulka s obsahem

User Guide

RapidIO MegaCore Function

Contents

Contents v

Chapter 5. Signals

Chapter 6. Software Interface

Chapter 7. Testbenches

Releases

RapidIO IP Core Features

Features

Device Family Support

Note to Table 1–2:

Interoperability Testing

Note to Table 1–4:

Notes to Table 1–7:

Notes to Table 1–8:

Installation and Licensing

2. Getting Started

Simulating IP Cores

Calibration Clock

Transceiver Settings

IV GX Variations

External Transceiver PLL

Specifying Constraints

Variations

Core Instances

Mode Selection

Transceiver Selection

Baud Rate

Reference Clock Frequency

Receive Buffer Size

Transmit Buffer Size

Enable 16-Bit Device ID Width

Destination ID Checking

Maintenance Logical Layer

Port Write Tx Enable

Port Write Rx Enable

Avalon-MM Master

Avalon-MM Slave

Doorbell Slave

Device ID

Vendor ID

Revision ID

Processing Element Features

Switch Support

Enable Switch Support

Number of Ports

Port Number

Source Operation

Destination Operation

4. Functional Description

Interfaces

Avalon System Clock

Reference Clock

Other Input Clocks

Clock Domains

Notes to Figure 4–2:

Notes to Table 4–2:

Reset for RapidIO IP Cores

Reset Controller

Clocking and Reset Structure

Physical Layer

Physical Layer Architecture

Receiver Transceiver

CRC Checking and Removal

Transmitter Transceiver

Physical Layer Receive Buffer

Transport Layer

Receiver

Transaction ID Ranges

Concentrator Register Module

Maintenance Module

Maintenance Register

Maintenance Slave Processor

Maintenance Master Processor

Port-Write Processor

Registers Location

Transactions

Notes to Table 4–8:

Notes to Table 4–9:

Note to Figure 4–22:

Notes to Table 4–11:

Notes to Table 4–12:

Note to Table 4–13:

Notes to Table 4–14:

Doorbell Module Block Diagram

Preserving Transaction Order

100

Doorbell Message Generation

101

Doorbell Message Reception

102

Note to Figure 4–30:

103

29’hb4b5959

104

CRC field is not removed

105

Note to Table 4–15:

105

Logical Layer Modules

106

Protocol Violations

108

Fatal Errors

108

Maintenance Avalon-MM Slave

109

Maintenance Avalon-MM Master

110

Port-Write Reception Module

111

Input/Output Avalon-MM Slave

111

Input/Output Avalon-MM Master

112

Note to Table 5–2:

115

5–2 Chapter 5: Signals

116

Physical Layer Signals

116

Multicast Event Signals

117

Note to Table 5–6:

118

Notes to Table 5–7:

118

Chapter 5: Signals 5–5

119

5–6 Chapter 5: Signals

120

Notes to Table 5–8:

121

5–8 Chapter 5: Signals

122

Chapter 5: Signals 5–9

123

124

Avalon-MM Interface Signals

124

Chapter 5: Signals 5–11

125

4x variations

126

2x and 4x variations

126

Chapter 5: Signals 5–13

127

Note to Table 5–19:

128

Notes to Table 5–20:

129

5–16 Chapter 5: Signals

130

Notes to Table 5–21:

131

5–18 Chapter 5: Signals

132

6. Software Interface

133

Physical Layer Registers

136

Note to Table 6–10:

141

Note to Table 6–11:

143

Note to Table 6–12:

143

Note to Table 6–13:

144

Note to Table 6–14:

144

Note to Table 6–15:

144

Note to Table 6–16:

145

Note to Table 6–17:

145

Notes to Table 6–18:

146

Notes to Table 6–19:

147

Note to Table 6–22:

148

Note to Table 6–23:

148

Note to Table 6–24:

148

Receive Maintenance Registers

149

Transmit Port-Write Registers

150

Receive Port-Write Registers

151

Note to Table 6–45:

154

Note to Table 6–51:

156

Doorbell Message Registers

158

Note to Table 6–63:

160

7. Testbenches

163

7–2 Chapter 7: Testbenches

164

Chapter 7: Testbenches 7–3

165

7–4 Chapter 7: Testbenches

166

SWRITE Transactions

167

NWRITE_R Transactions

168

NWRITE Transactions

169

NREAD Transactions

170

Doorbell Transactions

170

Chapter 7: Testbenches 7–9

171

Port-Write Transactions

172

Chapter 7: Testbenches 7–11

173

7–12 Chapter 7: Testbenches

174

8. Qsys Design Example

175

Running Qsys

177

Adding the Master I/O BFM

181

Adding the On-Chip Memory

182

Connecting Unconnected Clocks

183

Connecting System Components

183

Generating the System

185

Simulating the System

186

A. Initialization Sequence

187

Additional Information

193

Info–2 Additional Information

194

Document Revision History

194

Additional Information Info–3

195

Info–4 Additional Information

196

Note to Table:

197

Typographic Conventions

198

Info–6 Additional Information

198

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Altera RapidIO MegaCore Function manuály

Altera RapidIO MegaCore Function Uživatelský manuál (198 strany)

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