Altera Nios II Embedded Evaluation Kit Cyclone III Editio Uživatelský manuál stáhnout pdf (Strana 29)

3–5 Development Board Version 1.0. Altera Corporation

Nios II Embedded Evaluation Kit, Cyclone III Edition July 2010

Where to find the Nios II Processor Systems

System Functions

■ PLL—The PLL accepts the global input clock source from the

50-MHz on-board oscillator and generates the following clocks

● 100-MHz CPU Clock

● 100-MHz SSRAM Clock

● 66.5-MHz DDR SDRAM Clock

● 60-MHz Peripheral Clock (“slow peripherals”)

● 40-MHz Remote System Update Clock

■ System Clock Timer—General purpose system timer.

■ Performance Counter—Counter used for debug and system

performance analysis.

■ System ID—Used to sync the hardware system generation with the

software generation tools.

■ Remote System Update Block—Used for automatic configuration at

boot-time from the on-board active parallel flash. The Nios II

processor writes reset address of the hardware system stored in flash

for reconfiguration.

■ LED PIO—Output only control block for LED1-LED4

■ Pushbutton PIO—Input only control block for the on-board

pushbuttons.

■ PIO for ID EEPROM (I2C)—Used to communicate with the

EEPROM ID chip which stores information about the board

including the touch panel calibration data and Ethernet MAC

address.

1 The I2C interface is implemented using software and general

purpose I/Os connected to the Nios II Standard System.

Memory Interface

There are four different types of on-board memory or storage devices.

The memory controllers for three of these devices are provided as part of

Altera’s IP Suite and include:

■ SSRAM Controller

■ DDR SDRAM Controller

■ CFI Flash Controller

■ SD Card

1 The controller, API, and FAT File System for the SD-Card used

in the Nios II Standard System is provided under license

agreement by El Camino (http://www.elcamino.de)

1 2 ... 24 25 26 27 28 29 30 31 32 33 34 ... 79 80

Žádné komentáře

Altera Nios II Embedded Evaluation Kit Cyclone III Editio Uživatelský manuál Strana 29