Altera LVDS SERDES Transmitter / Receiver Uživatelský manuál stáhnout pdf (Strana 39)

Parameter Type Description

reset_fifo_at_first_lock String Specifies when the bit-serial FIFO resets.

Normally, the bit-serial FIFO is reset when the

DPA circuitry is locked or reset through the rx_

reset port. The rx_dpa_locked port and the

enable_dpa_mode parameter must be enabled if

this parameter is specified. The values are ON

and OFF. If omitted, the default value is ON. Only

available for Arria GX, Arria II GX, Arria II GZ,

Stratix II and Stratix II GX devices.

rx_align_data_reg String Controls byte alignment circuitry. If omitted,

the default value is RISING_EDGE. This port is

available for Stratix III devices only.

use_coreclock_input String Indicates whether the rx_coreclk port or the

clock from PLL is used as the non-peripheral

clock. You must connect the rx_coreclk port

if you turn on this parameter. The values are ON

and OFF. If omitted, the default value is OFF.

This parameter is only available for Stratix GX

devices. This parameter is available in DPA

mode only.

use_external_pll String Specifies whether the ALTVDS_RX IP core

generates a PLL or connect to a user-specified

PLL. Altera recommends instantiating the

external PLL with the parameter editor. Only

available for Arria GX, Arria II GX, Arria II GZ,

Arria V, Arria V GZ, Cyclone, Cyclone II,

Cyclone III, Cyclone IV, HardCopy II,

HardCopy III, HardCopy IV, Stratix, Stratix

GX. Stratix II, Stratix II GX, Stratix III, Stratix

IV, and Stratix V devices. This option is not

available when using deserialization factor of 1

and 2 in the Cyclone series.

use_no_phase_shift

String The values are ON and OFF. If omitted, default

value is ON. Altera recommends setting this

parameter to OFF unless you have done a phase

adjustment. When set to OFF, a phase shift of

90° is added to the clock to center the clock in

the data. Use this parameter when the pll_

operation_mode parameter value is set to

SOURCE_SYNCHRONOUS for Cyclone II and Stratix

II devices.

Related Information

• on page 67

UG-MF9504

2014.12.15

Command Line Interface Parameters

LVDS SERDES Transmitter/Receiver IP Cores User Guide

Altera Corporation

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