
2–25 Altera Corporation
LCD Multimedia HSMC August 2008
Interfaces/ Connectors
Figure 2–14 shows the Video Decoder interface schematic.
Figure 2–14. Video Decoder Interface Schematic
NTSC PAL Video Decoder Circuit
Uses the ADV7180 Multi-format SDTV Video Decoder
■ Supports worldwide NTSC/PAL/SECAM color demodulation
■ One 10-bit ADC, 4X over-sampling for CVBS
■ Supports Composite Video (CVBS) RCA jack input
■ Supports digital output formats: 8-bit ITU-R BT.656 YCrCb 4:2:2
HC_TD_HS
86 H13 T11
TD_HS
39 Video Decoder H_SYNC
Notes:
(1) These signals do not go through the MAX II chip. They pass through the MAX3378 level translator chip, U10.
Table 2–18. Video Decoder Pinout with HSMC Connector
HSMC Connector MAX II Video Decoder
Signal Name
Pin
No.
HSMC
Connector
Side Pin
Device
Side Pin
Signal Name
Pin
No.
Description
28MHz
28MHz
CVBS1_IN
TD_D0
TD_D1
TD_D2
TD_D3
TD_D4
TD_D5
TD_D6
TD_D7
TD_D[0..7]
27MHZ
TD_HS
TD_VS
I2C_SDAT
I2C_SCLK
TD_RESET
VCC33
V_AGND
AV_VCC18VCC18
VCC33
PV_VCC18
V_AGND
VCC33
I2C ADDRESS IS 0x40
R64 36R64 36
R67 120R67 120
RN2 47RN2 47
1
2
3
4
5
6
7
89
10
11
12
13
14
15
16
C47
10N
C47
10N
BC38
0.1U
BC38
0.1U
U8
ADV7180
U8
ADV7180
HS
39
DGND
3
XTAL1
12
XTAL
13
DVDD
14
DGND
35
P1
16
P0
17
P4
8
P3
9
P2
10
LLC
11
P5
7
P6
6
P7
5
INTRQ
38
DVDDIO
1
DVDDIO
4
DGND
15
SFL
2
PWRDWN
18
PVDD
20
AGND
21
DGND
40
AIN1
23
AIN2
29
AGND
24
TEST_0
22
VREFP
25
AVDD
27
AGND
28
VREFN
26
AIN3
30
RESET
31
ALSB
32
SDATA
33
SCLK
34
DVDD
36
VS/FIELD
37
ELPF
19
EXPOSED
41
R63
1.74K
R63
1.74K
J11
RCA JACK
J11
RCA JACK
R65 39R65 39
C49 0.1UC49 0.1U
C50 0.1UC50 0.1U
C48 0.1UC48 0.1U
C51
0.1U
C51
0.1U
Y3
28.63636MHz
Y3
28.63636MHz
VCC
4
OUT
3
GND
2
EN
1
R66 120R66 120
C52 0.1UC52 0.1U
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