
4–4 Chapter 4: Development Board Setup
Factory Default Switch Settings
DSP Development Kit, Stratix V Edition July 2013 Altera Corporation
User Guide
2. Set the DIP switch bank (SW3) to match Table 4–2 and Figure 4–2.
f For details on the JTAG chain, refer to the DSP Development Kit, Stratix V
Edition Reference Manual. For USB-Blaster II configuration details, refer to the
On-Board USB-Blaster II page.
3. Set DIP switch bank (SW4) to match Table 4–3 and Figure 4–2.
Table 4–2. SW3 JTAG DIP Switch Settings
(1)
Switc
h
Board
Label
Function
Default
Position
1 MAX_JTAG_EN
Switch 1 has the following options:
■ When on (0), removes the MAX V system controller in
the JTAG chain.
■ When off (1), includes the MAX V system controller
from the JTAG chain.
Off
2 HSMA_JTAG_EN
Switch 2 has the following options:
■ When on (0), removes the HSMC Port A in the JTAG
chain.
■ When off (1), includes the HSMC Port A from the JTAG
chain.
On
3 HSMB_JTAG_EN
Switch 3 has the following options:
■ When on (0), removes the HSMC Port B in the JTAG
chain.
■ When off (1), includes the HSMC Port B from the JTAG
chain.
On
4 PCIE_JTAG_EN
Switch 4 has the following options:
■ When on (0), removes the PCI Express Edge connector
from the JTAG chain.
■ When off (1), includes the PCI Express Edge connector
in the JTAG chain.
On
Note to Table 4–2:
(1) If you plug in an external USB-Blaster cable to the JTAG header (J10), the On Board USB-Blaster II is disabled. The
JTAG chain is normally mastered by the on-board USB-Blaster II.
Table 4–3. SW4 MSEL DIP Switch Settings
(1)
Switch
Board
Label
Function
Default
Position
1 MSEL0 Configuration Setting 0 On (0)
2 MSEL1 Configuration Setting 1 On (0)
3 MSEL2 Configuration Setting 2 On (0)
4 MSEL3 Configuration Setting 3 Off (1)
5 MSEL4 Configuration Setting 4 On (0)
6 — — On (0)
Note to: Table 4–3
(1) Set MSEL[4:0] to valid configuration schemes as listed in the Stratix V Device
Handbook.
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