Altera Cyclone II EP2C35 PCI Development Board Uživatelský manuál stáhnout pdf (Strana 15)

Altera Corporation Core Version 4.0.0 2–5

May 2005 Cyclone II EP2C35 PCI Development Board Reference Manual

Board Components & Interfaces

PCI Operating Mode, Speed & DIP Switch Settings

Tables 2–3, 2–4, and 2–5 list the board’s PCI operating mode and speed,

and the corresponding DIP switch (S4) bank setting.

Memory

The board has the following memory components:

■ Two 32-MByte DDR2 SDRAM devices

■ Two EPCS64 serial configuration (flash) devices

DDR2 SDRAM Memory

The board was tested with the Altera 167-MHz, DDR2 SDRAM Controller

MegaCore function version 3.2.0. Two 16M × 16 DDR2 SDRAM devices

are connected to banks 3 and 4 of the Cyclone II device as a single

16M × 32 memory block.

EPCS64 Serial Configuration (Flash) Devices

The board has two EPCS64Sl16N serial configuration devices (U7 and

U19) that upon power-up programs the Cyclone II device. The board

contains one EPCS64Sl16N device that is user-programmable, and one

preloaded, factory-programmed EPCS64Sl16N device.

Table 2–3. PCI Operating Mode Setting

DIP Switch Position 1 (PCI Mode) PCI Operating Mode

Off PCI-X at the speed shown in Table 2–5.

On PCI at the speed shown in Table 2–4.

Table 2–4. PCI Operating Speed Setting

DIP Switch Position 3 (PCI SPD) PCI Operating Speed (MHz)

Off 66 MHz

On 33 MHz

Table 2–5. PCI-X Operating Speed Setting

DIP Switch Position 2 (PCI XSPD) PCI-X Operating Speed (MHz)

Off 133 or 100 MHz

On 66 MHz

1 2 ... 10 11 12 13 14 15 16 17 18 19 20 ... 49 50

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Altera Cyclone II EP2C35 PCI Development Board Uživatelský manuál Strana 15