Altera Arria V GX FPGA Development Board Uživatelský manuál stáhnout pdf (Strana 50)

2–40 Chapter 2: Board Components

Components and Interfaces

Arria V GX FPGA Development Board November 2013 Altera Corporation

Reference Manual

10/100/1000 Ethernet

This development board supports 10/100/1000 base-T Ethernet using an external

Marvell 88E1111 PHY and Altera Triple-Speed Ethernet MegaCore MAC function. The

PHY-to-MAC interface employs RGMII using the Arria V GX FPGA LVDS pins in

Soft-CDR mode at 1.25 Gbps transmit and receive. In 10-Mb or 100-Mb mode, the

RGMII interface still runs at 1.25 GHz but the packet data is repeated 10 or 100 times.

The MAC function must be provided in the FPGA for typical networking

applications.

The Marvell 88E1111 PHY uses 2.5-V and 1.0-V power rails and requires a 25 MHz

reference clock driven from a dedicated oscillator. The PHY interfaces to a HALO

HFJ11-1G02E model RJ45 with internal magnetics that can be used for driving copper

lines with Ethernet traffic.

Figure 2–9 shows the RGMII interface between the FPGA (MAC) and Marvell 88E1111

PHY.

Table 2–43 lists the Ethernet PHY interface pin assignments.

Figure 2–9. RGMII Interface between FPGA (MAC) and Marvell 88E1111 PHY

10/100/1000 Mbps

Ethernet MAC

Marvell 88E1111

PHY

Device

Transformer

RJ45

RGMII Interface

TXD[3:0]

RXD[3:0]

Table 2–43. Ethernet PHY Pin Assignments, Signal Names and Functions (Part 1 of 2)

Board

Reference

(U14)

Schematic Signal Name

Arria V GX FPGA

Pin Number

I/O Standard Description

ENET_GTX_CLK

AN16 2.5-V CMOS RGMII transmit clock

ENET_INTN

AP16 2.5-V CMOS Management bus interrupt

ENET_LED_DUPLEX

— 2.5-V CMOS Duplex link LED

ENET_LED_DUPLEX

— 2.5-V CMOS Duplex link LED

ENET_LED_LINK10

— 2.5-V CMOS 10-Mb link LED

ENET_LED_LINK100

— 2.5-V CMOS 100-Mb link LED

ENET_LED_LINK1000

AN17 2.5-V CMOS 1000-Mb link LED

ENET_LED_RX

— 2.5-V CMOS RX data active LED

ENET_LED_RX

— 2.5-V CMOS RX data active LED

ENET_LED_TX

— 2.5-V CMOS TX data active LED

ENET_MDC

AJ18 2.5-V CMOS Management bus data clock

ENET_MDIO

AL17 2.5-V CMOS Management bus data

1 2 ... 45 46 47 48 49 50 51 52 53 54 55 ... 89 90

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