Altera Arria V GT FPGA Development Board Uživatelský manuál stáhnout pdf (Strana 7)

Chapter 1: Overview 1–3

Board Component Blocks

December 2014 Altera Corporation Arria V GT FPGA Development Board

Reference Manual

■ Mechanical

■ PCI Express long form factor (4.376” x 10.45”)

■ PCI Express chassis or bench-top operation

Dual FPGA

The development board includes two Arria V GT FPGAs that connect to other

components on the board to provide a better transceiver and bandwidth design

solution.

FPGA 1

The first FPGA device (FPGA 1) connects to the following components:

■ Communication ports

■ One PCI Express x8 edge connector

■ One universal HSMC expansion port (port A)

■ One USB 2.0 connector

■ One gigabit Ethernet port

■ Chip-to-Chip (C2C) bridge with 29 LVDS inputs and 29 LVDS outputs, and x8

transceivers

■ Two small form factor pluggable plus (SFP+) channels

■ One SMA 10 Gbps transceiver channel

■ Three Bull’s Eye 10 Gbps transceiver channels

■ Memory

■ 1152-Mbyte (MB) DDR3 SDRAM with a 72-bit data bus

■ 72-Mbit (Mb) QDRII+ SRAM

■ 1-Gbit (Gb) synchronous flash with a 16-bit data bus

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Altera Arria V GT FPGA Development Board Uživatelský manuál Strana 7