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2–42 Chapter 2: Board Components
Components and Interfaces
Arria V GT FPGA Development Board December 2014 Altera Corporation
Reference Manual
Table 227 lists the HSMC port B interface pin assignments, signal names, and
functions.
156
HSMA_CLK_IN_P2
AR6 LVDS or 2.5-V LVDS or CMOS clock in 2 or CMOS bit 77
157
HSMA_CLK_OUT_N2
AL7 LVDS or 2.5-V LVDS or CMOS clock out 2 or CMOS bit 78
158
HSMA_CLK_IN_N2
AP6 LVDS or 2.5-V LVDS or CMOS clock in 2 or CMOS bit 79
160
HSMA_PSNTN
AW15 2.5-V CMOS HSMC port A presence detect
Table 2–26. HSMC Port A Pin Assignments, Schematic Signal Names, and Functions (Part 5 of 5)
Board
Reference (J1)
Schematic Signal Name
Arria V GT
FPGA
Pin Number
I/O Standard Description
Table 2–27. HSMC Port B Pin Assignments, Schematic Signal Names, and Functions (Part 1 of 4)
Board
Reference (J2) Schematic Signal Name
Arria V GT
FPGA
Pin Number
I/O Standard Description
17
HSMB_TX_P3
AT3 1.5-V PCML Transceiver TX bit 3
18
HSMB_RX_P3
AU1 1.5-V PCML Transceiver RX bit 3
19
HSMB_TX_N3
AT4 1.5-V PCML Transceiver TX bit 3n
20
HSMB_RX_N3
AU2 1.5-V PCML Transceiver RX bit 3n
21
HSMB_TX_P2
AP3 1.5-V PCML Transceiver TX bit 2
22
HSMB_RX_P2
AR1 1.5-V PCML Transceiver RX bit 2
23
HSMB_TX_N2
AP4 1.5-V PCML Transceiver TX bit 2n
24
HSMB_RX_N2
AR2 1.5-V PCML Transceiver RX bit 2n
25
HSMB_TX_P1
AM3 1.5-V PCML Transceiver TX bit 1
26
HSMB_RX_P1
AN1 1.5-V PCML Transceiver RX bit 1
27
HSMB_TX_N1
AM4 1.5-V PCML Transceiver TX bit 1n
28
HSMB_RX_N1
AN2 1.5-V PCML Transceiver RX bit 1n
29
HSMB_TX_P0
AK3 1.5-V PCML Transceiver TX bit 0
30
HSMB_RX_P0
AL1 1.5-V PCML Transceiver RX bit 0
31
HSMB_TX_N0
AK4 1.5-V PCML Transceiver TX bit 0n
32
HSMB_RX_N0
AL2 1.5-V PCML Transceiver RX bit 0n
33
HSMB_SDA
AG25 2.5-V CMOS Management serial data
34
HSMB_SCL
AH26 2.5-V CMOS Management serial clock
35
JTAG_TCK
AV34 2.5-V CMOS JTAG clock signal
36
HSMB_JTAG_TMS
2.5-V CMOS JTAG mode select signal
37
HSMB_JTAG_TDO
2.5-V CMOS JTAG data output
38
HSMB_JTAG_TDI
2.5-V CMOS JTAG data input
39
HSMB_CLK_OUT0
AJ33 LVDS or 2.5-V Dedicated CMOS clock out
40
HSMB_CLK_IN0
AR6 LVDS or 2.5-V Dedicated CMOS clock in
41
HSMB_D0
AW25 2.5-V CMOS Dedicated CMOS I/O bit 0
42
HSMB_D1
AW26 2.5-V CMOS Dedicated CMOS I/O bit 1
43
HSMB_D2
AV25 2.5-V CMOS Dedicated CMOS I/O bit 2
44
HSMB_D3
AV24 2.5-V CMOS Dedicated CMOS I/O bit 3
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