Altera Arria V Avalon-MM Uživatelský manuál Strana 104
- Strana / 166
- Tabulka s obsahem
- KNIHY
Hodnocené. / 5. Na základě hodnocení zákazníků
Link Width Maximum Link Rate Avalon Interface Width coreclkout_hip
×2
Gen2 64
125 MHz
×4 Gen2 128 125 MHz
pld_clk
coreclkout_hip can drive the Application Layer clock along with the pld_clk input to the IP core. The
pld_clk can optionally be sourced by a different clock than coreclkout_hip. The pld_clk minimum
frequency cannot be lower than the coreclkout_hip frequency. Based on specific Application Layer
constraints, a PLL can be used to derive the desired frequency.
Clock Summary
Table 6-3: Clock Summary
Name Frequency Clock Domain
coreclkout_hip
62.5, 125 or 250 MHz Avalon-ST interface between the Transaction and
Application Layers.
pld_clk
62.5, 125, or 250 MHz Application and Transaction Layers.
refclk 100 or 125 MHz SERDES (transceiver). Dedicated free running input
clock to the SERDES block.
reconfig_xcvr_clk
100 –125 MHz Transceiver Reconfiguration Controller.
UG-01105_avmm
2014.12.15
pld_clk
6-7
Reset and Clocks
Altera Corporation
Send Feedback
- User Guide 1
- Datasheet 2
- Features 3
- Release Information 6
- Device Family Support 6
- Altera FPGA 7
- IP Core Verification 9
- Debug Features 9
- Recommended Speed Grades 10
- Hard IP for PCI Express 12
- Running Qsys 13
- Generating the Example Design 14
- Programming a Device 18
- Quartus II Programmer 19
- Parameter Settings 20
- Parameter Value Description 21
- Device Capabilities 23
- Error Reporting 24
- Link Capabilities 25
- MSI and MSI-X Capabilities 25
- Power Management 27
- Subscribe 31
- RX Avalon-MM Master Signals 33
- Clock Signals 38
- Reset Signals 38
- Signal Direction Description 39
- Hard IP Status 40
- IntxReq_i 44
- IntAck_o 44
- Hard IP Status Extension 46
- Field and Bit Map 54
- 0134678951 54
- Serial Interface Signals 55
- 9 Ch 18 Ch 56
- Variant Data CMU Clock 57
- PIPE Interface Signals 58
- Test Signals 62
- Registers 63
- Altera-Defined VSEC Registers 71
- CvP Registers 72
- Address Range Register 76
- Bit Name Access Description 77
- Bits Name Access Description 78
- PCI Express Mailbox Registers 79
- Avalon-MM Mailbox Registers 83
- Address Name Access 84
- Description 84
- Byte Offset 84
- Register Dir Description 84
- Sending a Write TLP 90
- Root Port TLP Data Registers 92
- Bits Register Description 95
- Reset and Clocks 98
- Example Design 99
- UG-01105_avmm 100
- 2014.12.15 100
- Clock Domains 102
- Data Rate Frequency 103
- Related Information 103
- Clock Summary 104
- Interrupts for Endpoints 105
- MSI/MSI‑X Support 107
- Qsys System 108
- Error Handling 109
- Physical Layer Errors 110
- Data Link Layer Errors 110
- Transaction Layer Errors 111
- Error Type Description 112
- Status Bit Conditions 115
- IP Core Architecture 117
- Hard IP for PCI Express 118
- Clocks and Reset 119
- Transceiver Reconfiguration 119
- Interrupts 119
- Data Link Layer 120
- Altera Corporation 121
- Send Feedback 121
- Physical Layer 122
- TX Packets 123
- Avalon‑MM Bridge TLPs 127
- Byte Enable Value Description 128
- PCI Express Avalon-MM Bridge 130
- RX Block 136
- Avalon-MM RX Master Block 136
- TX Block 137
- Interrupt Handler Block 137
- Design Implementation 139
- Making Pin Assignments 140
- Optional Features 141
- ECRC on the RX Path 142
- ECRC on the TX Path 143
- Enable PLL calibration 145
- Debugging 148
- Setting Up Simulation 149
- Use Third-Party PCIe Analyzer 150
- BIOS Enumeration Issues 151
- Address[31:2] 152
- Figure A-6: I/O Read Request 154
- 7 6 5 4 3 2 1 0 158
- Core Config 8 4 1 158
- Additional Information 160
- Date Version Changes Made 161
- How to Contact Altera 163
- Typographic Conventions 164
- Visual Cue Meaning 165
Související produkty a manuály pro Měřící nástroje Altera Arria V Avalon-MM
Měřící nástroje Altera DDR3 SDRAM High-Performance Controller and ALTMEMP Uživatelský manuál
(10 stránky)
(10 stránky)
Měřící nástroje Altera DDR SDRAM High-Performance Controllers and ALTMEMP Uživatelský manuál
(140 stránky)
(140 stránky)
Měřící nástroje Altera Floating-Point Uživatelský manuál
(157 stránky)
(157 stránky)
Měřící nástroje Altera JESD204B IP Uživatelský manuál
(158 stránky)
(158 stránky)
Měřící nástroje Altera Nios II Embedded Evaluation Kit Cyclone III Editio Uživatelský manuál
(3 stránky)
(3 stránky)
© 2020, manymanuals.cz. Všechna práva vyhrazena. | 0.085 s |
Manymanuals.com
Manymanuals.de
Manymanuals.fr
Manymanuals.it
Manymanuals.pl
Manymanuals.cz
Manymanuals.es
Manymanuals-pt.com
Komentáře k této Příručce