Altera ALTDLL Uživatelský manuál Strana 69
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4–33 Chapter 4: Functional Description
ALTDQ_DQS Megafunction Ports
ALTDLL and ALTDQ_DQS Megafunctions User Guide © February 2012 Altera Corporation
ALTDQ_DQS Megafunction Ports
Table 4–11 to Table 4–19 describes the ports of the ALTDQ_DQS megafunction that
you can use to configure the DQS input path, DQS output path, DQS OE path,
DQ/DQS OCT path, DQ input path, DQ output path, DQ OE path, DQSN IO path,
and DQS_CONFIG/IO_CONFIG path.
DQS Input Path Megafunction Ports
Table 4–11 summarizes all the ports on the megafunction to configure the DQS input
path.
n
b
= number of bidirectional DQ
n
o
= number of output DQ
n
i
= number of input DQ
n
c
= number of clock divider
Table 4–11. Megafunction Ports to Configure DQS Input Path (Part 1 of 2)
Port Name Type
Optional/
Required Default Description
core_delayctrlin[5..0] Input Optional GND This port receives the Gray-coded delay chain setting
for the DQS read path from the FPGA core. This port
does not need to match the polarity of its source and
can be inverted.
dll_delayctrlin[5..0] Input Optional GND This port receives the Gray-coded delay chain setting
for the DQS read path from the
ALTDLL:delayctrlout[5..0] port. This port
must match the polarity of its source and cannot be
inverted.
dqs_bus_out Output Optional — This port receives the possibly delayed DQS output
signal from the DQS_ENABLE:dqsbusout,
DQSBUSOUT_DELAY_CHAIN:dataout, or
DQS_DELAY_CHAIN:dqsbusout port.
dqs_enable_ctrl_clk Input Optional V
CC
This port is connected to the
DQS_ENABLE_CTRL:clk port that is used to
capture the DQS_ENABLE_CTRL:dqsenablein
signal.
dqs_enable_ctrl_hr_
datainhi
Input Optional GND This port is connected to the
DQS_ENABLE_CTRL_HR_DDIO_OUT:datainhi
port. This port receives the half-rate data for the rising
edge of the IO_CLOCK_DIVIDER:clkout signal.
dqs_enable_ctrl_hr_
datainlo
Input Optional GND This port is connected to the
DQS_ENABLE_CTRL_HR_DDIO_OUT:datainlo
port. This port receives the half-rate data for the falling
edge of the IO_CLOCK_DIVIDER:clkout signal.
dqs_enable_ctrl_in Input Optional V
CC
This active-high port is connected to the
DQS_ENABLE_CTRL:dqsenablein port that is
used to enable or disable the
DQS_ENABLE_CTRL:dqsenableout port.
- ALTDLL and ALTDQ_DQS 1
- Megafunctions User Guide 1
- UG-01032-5.0 2
- Contents 3
- 1. About these Megafunctions 5
- Features 6
- 2. Getting Started 7
- ALTOCT Megafunction 8
- Customized Controller Logic 8
- Simulate the Design 9
- Create Timing Constraints 9
- Adjust Constraints 10
- Generate the Megafunctions 11
- Settings Value 13
- Turned off 14
- Enable DQS delay chain 14
- 3. Parameter Settings 19
- [5..0] output port 20
- ALTDLL Parameter Editor 21
- ALTDQ_DQS Parameter Editor 23
- Reset/Config Ports 26
- ports on the megafunction 27
- — DQS_OFFSETCTRL_ 27
- inputs to be registered by 28
- signals of 28
- “DQ Input Path” on page 4–8 29
- 4. Functional Description 37
- ■ DQS Input Path 38
- ■ DQ Input Path 38
- ■ DQ Output/OE Path 38
- ■ DQS Output/OE Path 38
- ■ DQ/DQS OCT Path 38
- ALTDLL Megafunction 39
- ALTDQ_DQS Megafunction 40
- DQS Input Path 42
- DQ Input Path 44
- DQ Output/OE Path 46
- DQS Output/OE Path 48
- DQ/DQS OCT Path 50
- Delay Chains 51
- Deskew Delay Chains 52
- Note to Figure 4–13: 55
- Note to Figure 4–14: 55
- Note to Figure 4–15: 56
- Note to Figure 4–16: 56
- Note to Figure 4–17: 57
- DQS_CONFIG / IO_CONFIG Block 58
- ALTDLL Megafunction Ports 67
- ALTDQ_DQS Megafunction Ports 69
- DQ OE Path Megafunction Ports 78
- DQSn I/O Path Ports 79
- DQS_CONFIG/IO_CONFIG path 81
- RLDRAM interfaces 84
- Procedure 85
- 00 FF 00 FF 99
- ■ bidir_dq_io[0] 100
- A. Clear Box Generator 102
- Clear Box Generator Options 103
- Clear Box Parameters 104
- inputs are 108
- OUTPUT_DQ 114
- Additional Information 116
- Typographic Conventions 117
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