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10–4 Chapter 10: Low Latency PHY IP Core

General Options Parameters

Altera Transceiver PHY IP Core November 2012 Altera Corporation

User Guide

Bonding mode

×N

fb_compensation

Select ×N to use the same clock source for up to 6 channels in a

single transceiver bank, resulting in reduced clock skew. You

must use contiguous channels when you select ×N bonding. In

addition, you must place logical channel 0 in either physical

channel 1 or 4. Physical channels 1 and 4 are indirect drivers of

the ×N clock network.

Select fb_compensation (feedback compensation) to use the

same clock source for multiple channels across different

transceiver banks to reduce clock skew.

For more information about bonding, refer to “Bonded Channel

Configurations Using the PLL Feedback Compensation Path” in

Transceiver Clocking in Stratix V Devices in volume 2 of the

Stratix V Device Handbook.

FPGA fabric transceiver

interface width

8, 10, 16, 20, 32,

40, 50, 64, 66, 128

This option indicates the parallel data fabric transceiver interface

width. GT datapath supports a single width of 128 bits. Refer

toTable 10–4 for the supported interface widths of the Standard

and 10G datapaths.

PCS-PMA interface width

8, 10, 16, 20, 32,

30, 64

The PCS-PMA interface width depends on the FPGA fabric

transceiver interface width

and the Datapath type. Refer to

Table 10–4 for the supported interface widths of the Standard

and 10G datapaths.

PLL type

CMU

ATX

The CMU PLL is available for the Standard and 10G datapaths.

The ATX PLL is available for the Standard, 10G, and GT

datapaths. The CMU PLL has a larger frequency range than the

ATX PLL. The ATX PLL is designed to improve jitter performance

and achieves lower channel-to-channel skew; however, it

supports a narrower range of data rates and reference clock

frequencies. Another advantage of the ATX PLL is that it does not

use a transceiver channel, while the CMU PLL does.

An informational message displays in the message panel if the

PLL type that you select is not available at the frequency

specified.

Data rate Device dependent

Specifies the data rate in Mbps. Refer to Stratix V Device

Datasheet for the data rate ranges of datapath.

Base data rate

1 × Data rate

2 × Data rate

4 × Data rate

Select a bas

e data rate that minimizes the number of PLLs

required to generate all the clocks required for data transmission.

By selecting an appropriate base data rate, you can change data

rates by changing the divider used by the clock generation block.

For higher frequency data rates 2 × and 4× base data rates are not

available.

Input clock frequency Variable

Specifies the frequency of the PLL input reference clock. The

Input clock frequency drop down menu is populated with all valid

frequencies derived as a function of the data rate and base data

rate. However, if you select

fb_compensation

as the bonding

mode, then the input reference clock frequency is limited to the

(data rate)

 (PCS-PMA interface width).

Table 10–3. Low Latency PHY General Options

Name Value Description

1 2 ... 197 198 199 200 201 202 203 204 205 206 207 ... 483 484

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