Altera Nios II Specifikace

Nios II Classic Processor Reference GuideSubscribeSend FeedbackNII5V12015.04.02101 Innovation DriveSan Jose, CA 95134www.altera.com

• Optional memory management unit (MMU) to support operating systems that require MMUs• Optional memory protection unit (MPU)• Software development en

Instruction DescriptionldbioldbuiostbioldhioldhuiosthioThese operations load/store byte and half-word data from/to peripherals withoutcaching or buffe

Table 3-44: Move InstructionsInstruction Descriptionmovmovhimovimovuimoviamov copies the value of one register to another register. movi moves a 16-bi

Table 3-46: Shift and Rotate InstructionsInstruction DescriptionrolrorroliThe rol and roli instructions provide left bit-rotation. roli uses an immedi

Table 3-48: Conditional Branch InstructionsInstruction DescriptionbgebgeubgtbgtublebleubltbltubeqbneThese instructions provide relative branches that

Instruction DescriptionrdprswrprsThese instructions read and write a general-purpose registers between the currentregister set and another register se

Related InformationUnimplemented Instruction on page 3-45Document Revision HistoryTable 3-50: Document Revision HistoryDate Version ChangesApril 2015

Date Version ChangesSeptember 2004 1.1• Added details for new control register ctl5.• Updated details of debug and break processing to reflect newbeha

Instantiating the Nios II Processor42015.04.02NII51004SubscribeSend FeedbackThis chapter describes the Nios® II Processor parameter editor in Qsys. Th

Name DescriptionException VectorException vector memoryRefer to the "General Exception Vectors" section.Exception vector offsetException vec

Multiply and Divide SettingsThe Nios II/s and Nios II/f cores offer hardware multiply and divide options. You can choose the bestoption to balance emb

Figure 1-1: Example of a Nios II Processor System Nios IIProcessor Core SDRAMControllerOn-Chip ROMTristate bridge tooff-chip memorySystem Inter

General Exception VectorParameters in this section select the memory module where the general exception vector (exceptionaddress) resides, and the loc

Note: The Nios II MMU is optional and mutually exclusive from the Nios II MPU. Nios II systems caninclude either an MMU or MPU, but cannot include bot

Name DescriptionOmit data master portRefer to the "Data Master" Settings.Data cacheData cache line sizeBurst transfersData cache victim buff

Data Master SettingsThe Data Master parameters provide the following options for the Nios II/f core:• Omit data master port—Removes the Avalon-MM data

Name DescriptionIllegal instructionRefer to the "Exception Checking" section.Division errorMisaligned memory accessExtra exception informati

Related InformationSOPC Builder to Qsys Migration GuidelinesFor information about upgrading IDs that were manually-assigned values in Qsys, refer to t

Related Information• Programming Model on page 3-1• Programming ModelInterrupt Controller InterfacesThe Interrupt controller setting determines which

Related InformationAltera ASICsECCECC is only available for the Nios II/f core and provides ECC support for Nios II internal RAM blocks,such as instru

MMUWhen Include MMU on the Core Nios II tab is on, the MMU settings on the MMU and MPU Settingstab provide the following options for the MMU in the Ni

Related Information• Programming Model on page 3-1• Programming Model• Nios II Core Implementation Details on page 5-1• Nios II Core Implementation De

Because the pins and logic resources in Altera devices are programmable, many customizations arepossible:• You can rearrange the pins on the chip to s

Feature DescriptionHardwareBreakpointsSets a breakpoint on instructions residing in nonvolatile memory, such as flashmemory.Data Triggers Triggers bas

Debug Feature No Debug Level 1 Level 2 Level 3 Level 4(39)Download Software No Yes Yes Yes YesSoftware Breakpoints None Unlimited Unlimited Unlimited

Related InformationGeneral Exception Vector on page 4-4Advanced Debug SettingsDebug levels 3 and 4 support trace data collection into an on-chip memor

For information about converting SOPC Builder designs to Qsys, refer to the SOPC Builder to QsysMigration Guidelines.Related InformationSOPC Builder t

To add the floating-point custom instructions to the Nios II processor in Qsys, select Floating PointHardware under Custom Instruction Modules on the

Document Revision HistoryTable 4-9: Document Revision HistoryDate Version ChangesApril 2015 2015.04.02 Maintenance release.February 2014 13.1.0• Added

Date Version ChangesOctober 2005 5.1.0 Maintenance release.May 2005 5.0.0• Updates to reflect new GUI options in Nios II processor version5.0.• New de

Nios II Core Implementation Details52015.04.02NII51015SubscribeSend FeedbackThis document describes all of the Nios® II processor core implementations

FeatureCoreNios II/e Nios II/s Nios II/fData BusCache – – 512 bytes to 64 KBPipelined MemoryAccess– – –Cache Bypass Methods – –• I/O instructions• Bit

Related Information• Instruction Set Reference on page 8-1• Instruction Set ReferenceDevice Family SupportAll Nios II cores provide the same support f

Custom ComponentsYou can also create custom components and integrate them in Nios II processor systems. For perform‐ance-critical systems that spend m

The Nios II/f fast core is designed for high execution performance. Performance is gained at the expenseof core size. The base Nios II/f core, without

The Nios II/f core also provides a hardware divide option that includes LE-based divide circuitry in theALU.Including an ALU option improves the perfo

Shift and Rotate PerformanceThe performance of shift operations depends on the hardware multiply option. When a hardwaremultiplier is present, the ALU

Bit Fieldsline offsetTable 5-5: Cache Virtual Byte Address FieldsBit Fields31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16line15 14 13 12 11 10 9 8 7

Data CacheThe data cache memory has the following characteristics:• Direct-mapped cache implementation• Configurable line size of 4, 16, or 32 bytes•

Related Information• Instruction Set Reference on page 8-1• Instruction Set Reference• Processor Architecture on page 2-1• Processor ArchitectureBurst

The μTLBs are not visible to software. They act as an inclusive cache of the main TLB. The processor firstslook for a hit in the μTLB. If it misses, i

The A-stage stall occurs if any of the following conditions occurs:• An A-stage memory instruction is waiting for Avalon-MM data master requests to co

Instruction Cycles Penaltiesstore (without Avalon-MM transfer) 1store (with Avalon-MM transfer) > 1flushd, flushda (without Avalon-MM transfer) 2fl

• Division error• Fast translation lookaside buffer (TLB) miss (MMU only)• Double TLB miss (MMU only)• TLB permission violation (MMU only)• MPU region

• Simulate the behavior of a Nios II processor within your system.• Verify the functionality of your design, as well as evaluate its size and speed qu

• Instruction cache• ECC errors (1, 2, or 3 bits) that occur in the instruction cache are recoverable; the Nios II processorflushes the cache line and

Bit Field Description Effect onSoftwareAvailable15 Reserved16 Reserved17 Reserved18 Reserved19TLB_RERecoverable (1 bit) ECC error in TLB RAM (hardware

OverviewThe Nios II/s core:• Has an instruction cache, but no data cache• Can access up to 2 GB of external address space• Supports optional tightly-c

ALU Option Hardware Details Cycles per instruc‐tionSupported InstructionsEmbedded multiplieron Cyclone III familiesALU includes 32 x 16-bitmultiplier5

• Direct-mapped cache implementation• The instruction master port reads an entire cache line at a time from memory, and issues one read perclock cycle

Stage Letter Stage NameM MemoryW WritebackUp to one instruction is dispatched and/or retired per cycle. Instructions are dispatched and retired in-ord

Instruction Cycles PenaltiesBranch (correctly predictedtaken)2Branch (correctly predictednot taken)1Branch (mispredicted) 4 Pipeline flushtrap, break,

at the expense of execution performance. The Nios II/e core is roughly half the size of the Nios II/s core,but the execution performance is substantia

Instruction PerformanceThe Nios II/e core dispatches a single instruction at a time, and the processor waits for an instruction tocomplete before fetc

Document Revision HistoryTable 5-17: Document Revision HistoryDate Version ChangesApril 2015 2015.04.02 Obsolete devices removed (Stratix II, Cyclone

Date Version ChangesOctober 2005 5.1.0 Maintenance release.May 2005 5.0.0 Maintenance release.September 2004 1.1 Maintenance release.May 2004 1.0 Init

Nios II Processor Revision History62015.04.02NII51018SubscribeSend FeedbackEach release of the Nios® II Embedded Design Suite (EDS) introduces improve

Version Release Date Notes9.1 November2009• Added optional external interrupt controller interface.• Added optional shadow register sets.9.0 March 200

Architecture RevisionsArchitecture revisions augment the fundamental capabilities of the Nios II architecture, and affect allNios II cores. A change i

Version Release Date Notes1.01 September2004No changes.1.0 May 2004 Initial release of the Nios II processor architecture.Core RevisionsCore revisions

Version Release Date Notes5.1 SP1 January 2006 Bug Fix:Back-to-back store instructions can cause memory corruption to thestored data. If the first sto

Nios II/s CoreTable 6-4: Nios II/s Core RevisionsVersion Release Date Notes13.1 November2013• Added support for enhanced floating-point custom instruc

Version Release Date Notes1.1 December2004• Added user-configurable options affecting multiply and shiftoperations. Now designers can choose one of th

Version Release Date Notes6.1 November2006No changes.6.0 May 2006 No changes.5.1 October 2005 No changes.5.0 May 2005 Support for HardCopy devices (pr

Version Release Date Notes5.0 May 2005 Support for HardCopy devices (previous versions of the JTAG debugmodule did not support HardCopy devices).1.1 D

Date Version ChangesMarch 2009 9.0.0 Maintenance release.November 2008 8.1.0 Maintenance release.May 2008 8.0.0• Added MMU information.• Added MPU inf

Processor Architecture22015.04.02NII51002SubscribeSend FeedbackThis chapter describes the hardware structure of the Nios II processor, including a dis

Application Binary Interface72015.04.02NII51016SubscribeSend FeedbackThis chapter describes the Application Binary Interface (ABI) for the Nios® II pr

Memory AlignmentContents in memory are aligned as follows:• A function must be aligned to a minimum of 32-bit boundary.• The minimum alignment of a da

RegisterName Used byCompilerCalleeSaved(45)Normal Usager16 v vCallee-saved general-purpose registersr17 v vr18 v vr19 v vr20 v vr21 v vr22 v(46)r23 v(

StacksThe stack grows downward (i.e. towards lower addresses). The stack pointer points to the last used slot.The frame pointer points to the saved fr

Further Examples of StacksThere are a number of special cases for stack layout, which are described in this section.Stack Frame for a Function With al

Figure 7-3: Stack Frame Using Variable ArgumentsIn function a()Just prior to calling b()In function b()Just after executing prologueIncomingstackargum

Note: An even better way to find out what the prologue has done is to use information stored in theDWARF-2 debugging fields of the executable and link

The equivalent structure representing the arguments is:struct { int a; int b; };The first 16 bytes of the struct are assigned to r4 through r7. Theref

b(&value, i, j);}DWARF-2 DefinitionRegisters r0 through r31 are assigned numbers 0 through 31 in all DWARF-2 debugging sections.Object FilesTab

Name Value Overflowcheck(49)Relocated AddressRBit MaskMBit ShiftBR_NIOS2_LO16 10 No (S + A) & 0xFFFF 0x003FFFC0 6R_NIOS2_HIADJ16 11 No Adj(S+A) 0x

Figure 2-1: Nios II Processor Core Block DiagramExceptionControllerInternalInterruptControllerArithmeticLogic UnitGeneralPurposeRegisters Control Regi

Name Value Overflowcheck(49)Relocated AddressRBit MaskMBit ShiftBR_NIOS2_TLS_LDO16 30(50)Yes Refer to Thread-Local Storagesection0x003FFFC0 6R_NIOS2_T

Expressions in the table above use the following conventions:• S: Symbol address• A: Addend• PC: Program counter• GP: Global pointer• Adj(X): (((X >

R_NIOS2_GLOB_DATR_NIOS2_JUMP_SLOTR_NIOS2_RELATIVEA global offset table (GOT) entry referenced using R_NIOS2_GOT16, R_NIOS2_GOT_LO and/orR_NIOS2_GOT_HA

Copy RelocationThe R_NIOS2_COPY relocation is used to mark variables allocated in the executable that are defined in ashared library. The variable’s i

ldw r6, %tls_ldo(x2)(r2) # R_NIOS2_TLS_LDO16 x2# Value of x2 in r6One 2-word GOT slot is allocated for all R_NIOS2_TLS_LDM16 operations i

Linux Function CallsRegister r23 is reserved for the thread pointer on GNU Linux systems. It is initialized by the C library andit may be used directl

There are no floating-point exceptions. The optional floating point unit (FPU) does not supportexceptions and any process wanting exact IEEE conforman

The GOT pointer is loaded using a PC-relative offset to the _gp_got symbol, as shown below.Example 7-12: Loading the GOT Pointernextpc r221: orhi r1

The call and jmpi instructions are not available in position-independent code. Instead, all calls are madethrough the GOT. Function addresses may be l

Ltable: .word %gotoff(Label1) .word %gotoff(Label2) .word %gotoff(Label3)Related InformationProcedure Linkage Table on page 7-20Linux Program Lo

Implementation variables generally fit one of three trade-off patterns: more or less of a feature; inclusionor exclusion of a feature; hardware implem

The example below shows the PLT entry when the PLT GOT is close enough to the small data area for arelative jump.Example 7-22: PLT Entry Near Small Da

Example 7-25: Initial PLT Entry.PLTresolve: nextpc r14 orhi r13, r0, %hiadj(_GLOBAL_OFFSET_TABLE_) add r13, r13, r14 ldw r

provides intrinsic functions which perform the system call. Applications must use those functions ratherthan the system call directly. Atomic operatio

Date Version ChangesMay 2008 8.0.0• Frame pointer description updated.• Relocation table added.October 2007 7.2.0 Maintenance release.May 2007 7.1.0•

Instruction Set Reference82015.04.02NII51017SubscribeSend FeedbackThis section introduces the Nios® II instruction word format and provides a detailed

• A 6-bit opcode field OP• Three 5-bit register fields A, B, and C• An 11-bit opcode-extension field OPXIn most cases, fields A and B specify the sour

OP Instruction OP Instruction OP Instruction OP Instruction0x01 jmpi 0x11 0x21 0x310x02 0x12 0x22 0x32 custom0x03 ldbu 0x13 initda 0x23 ldbuio 0x33 in

Assembler Pseudo-InstructionsPseudo-instructions are used in assembly source code like regular assembly instructions. Each pseudo-instruction is imple

Assembler MacrosThe Nios II assembler provides macros to extract halfwords from labels and from 32-bit immediatevalues. These macros return 16-bit sig

Notation Meaning0xNNMM Hexadecimal notationX : Y Bitwise concatenation For example, (0x12 : 0x34) = 0x1234σ(X) The value of X after being sign-extende

Related Information• Programming Model on page 3-1• Programming Model• Instruction Set Reference on page 8-1• Instruction Set ReferenceArithmetic Logi

Exampleadd r6, r7, r8DescriptionCalculates the sum of rA and rB. Stores the result in rC. Usedfor both signed and unsigned addition.UsageCarry Detecti

Instruction FieldsA = Register index of operand rAB = Register index of operand rBC = Register index of operand rCBit Fields31 30 29 28 27 26 25 24 23

UsageCarry Detection (unsigned operands):Following an addi operation, a carry out of the MSB can bedetected by checking whether the unsigned sum is le

Bit Fields31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16A B IMM1615 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0IMM16 0x04andInstruction bitwise logical andOpe

DescriptionCalculates the bitwise logical AND of rA and (IMM16 : 0x0000)and stores the result in rB.ExceptionsNoneInstruction TypeIInstruction FieldsA

beqInstruction branch if equalOperationif (rA == rB)then PC ← PC + 4 + σ(IMM16)else PC ← PC + 4Assembler Syntaxbeq rA, rB, labelExamplebeq r6, r7, l

DescriptionIf (signed) rA >= (signed) rB, then bge transfers programcontrol to the instruction at label. In the instruction encoding,the offset giv

Instruction FieldsA = Register index of operand rAB = Register index of operand rBIMM16 = 16-bit signed immediate valueBit Fields31 30 29 28 27 26 25

Pseudo-instructionbgtu is implemented with the bltu instruction by swapping theregister operands.bleInstruction branch if less than or equal signedOpe

Assembler Syntaxblt rA, rB, labelExampleblt r6, r7, top_of_loopDescriptionIf (signed) rA < (signed) rB, then blt transfers program controlto the in

ContentsIntroduction... 1-1Nios II Processor Syst

Custom InstructionsThe Nios II architecture supports user-defined custom instructions. The Nios II ALU connects directly tocustom instruction logic, e

Instruction TypeIInstruction FieldsA = Register index of operand rAB = Register index of operand rBIMM16 = 16-bit signed immediate valueBit Fields31 3

Bit FieldsIMM16 0x1ebrInstruction unconditional branchOperationPC ← PC + 4 + σ(IMM16)Assembler Syntaxbr labelExamplebr top_of_loopDescriptionTransfer

ExamplebreakDescriptionBreaks program execution and transfers control to thedebugger break-processing routine. Saves the address of thenext instructio

Usagebret is used by debuggers exclusively and should not appear inuser programs, operating systems, or exception handlers.ExceptionsMisaligned destin

Bit Fields15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0IMM26 0callrInstruction call subroutine in registerOperationra ← PC + 4PC ← rAAssembler Syntaxcallr r

DescriptionIf rA == rB, then stores 1 to rC; otherwise, stores 0 to rC.Usagecmpeq performs the == operation of the C programminglanguage. Also, cmpeq

Instruction FieldsA = Register index of operand rAB = Register index of operand rBIMM16 = 16-bit signed immediate valueBit Fields31 30 29 28 27 26 25

cmpgeiInstruction compare greater than or equal signed immediateOperationif ((signed) rA >= (signed) σ(IMM16))then rB ← 1else rB ← 0Assembler Syn

DescriptionIf rA >= rB, then stores 1 to rC; otherwise stores 0 to rC.Usagecmpgeu performs the unsigned >= operation of the C program‐ming langu

Instruction FieldsA = Register index of operand rAB = Register index of operand rBIMM16 = 16-bit unsigned immediate valueBit Fields31 30 29 28 27 26 2

Table 2-2: Hardware Conformance with IEEE 754-1985 and IEEE 754-2008 Floating-Point StandardFeature Floating-Point HardwareImplementation with IEEE 75

DescriptionSign-extends the immediate value IMMED to 32 bits andcompares it to the value of rA. If rA > σ(IMMED), then cmpgtistores 1 to rB; otherw

Usagecmpgtui performs the unsigned > operation of the C program‐ming language. The maximum allowed value of IMMED is65534. The minimum allowed valu

Pseudo-instructioncmplei is implemented using a cmplti instruction with anIMM16 immediate value of IMMED + 1.cmpleuInstruction compare less than or eq

cmpltInstruction compare less than signedOperationif ((signed) rA < (signed) rB)then rC ← 1else rC ← 0Assembler Syntaxcmplt rC, rA, rBExamplecmpl

DescriptionSign-extends the 16-bit immediate value IMM16 to 32 bits andcompares it to the value of rA. If rA < σ(IMM16), then cmpltistores 1 to rB;

Instruction FieldsA = Register index of operand rAB = Register index of operand rBC = Register index of operand rCBit Fields31 30 29 28 27 26 25 24 23

cmpneInstruction compare not equalOperationif (rA != rB)then rC ← 1else rC ← 0Assembler Syntaxcmpne rC, rA, rBExamplecmpne r6, r7, r8DescriptionIf r

DescriptionSign-extends the 16-bit immediate value IMM16 to 32 bits andcompares it to the value of rA. If rA != σ(IMM16), then cmpneistores 1 to rB; o

UsageTo access a custom register inside the custom instruction logic,clear the bit readra, readrb, or writerc that corresponds to theregister field. I

DescriptionTreating rA and rB as signed integers, this instruction dividesrA by rB and then stores the integer portion of the resultingquotient to rC.

Feature Floating-Point HardwareImplementation with IEEE 754-1985Floating-Point Hardware 2Implementation with IEEE 754-2008NaNQuiet ImplementedNo disti

DescriptionTreating rA and rB as unsigned integers, this instructiondivides rA by rB and then stores the integer portion of theresulting quotient to r

DescriptionCopies the value of estatus into the status register, andtransfers execution to the address in ea.UsageUse eret to return from traps, exter

DescriptionIf the Nios II processor implements a direct mapped datacache, flushd writes the data cache line that is mapped to thespecified address bac

Bit FieldsIMM16 0x3bRelated Information• Cache and Tightly-Coupled Memory• flushda on page 8-40• initda on page 8-44• initd on page 8-43flushdaInstruc

UsageUse flushda to write dirty lines back to memory only if theaddressed memory location is currently in the cache, and thenflush the cache line. By

DescriptionIgnoring the tag, flushi identifies the instruction cache lineassociated with the byte address in rA, and invalidates that line.If the Nios

Bit Fields31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16A 0 0 0x0415 14 13 12 11 10 9 8 7 6 5 4 3 2 1 00x04 0 0x3ainitdInstruction initialize data ca

UsageUse initd after processor reset and before accessing datamemory to initialize the processor’s data cache. Use initd withcaution because it does n

DescriptionIf the Nios II processor implements a direct mapped datacache, initda clears the data cache line without checking for(or writing) a dirty d

Bit Fields31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16A 0 IMM1615 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0IMM16 0x13Related Information• Cache and Tightl

Related InformationNios II Custom Instruction User GuideFor more information about using floating-point custom instructions in software, refer to the

Bit Fields0x29 0 0x3aRelated InformationCache and Tightly-Coupled MemoryjmpInstruction computed jumpOperationPC ← rAAssembler Syntaxjmp rAExamplejmp

Usagejmpi is a low-overhead local jump. jmpi can transfer executionanywhere within the 256-MB range determined by PC31..28. TheNios II GNU linker does

ExceptionsSupervisor-only data addressMisaligned data addressTLB permission violation (read)Fast TLB miss (data)Double TLB miss (data)MPU region viola

DescriptionComputes the effective byte address specified by the sum of rAand the instruction's signed 16-bit immediate value. Loadsregister rB wi

Bit FieldsIMM16 0x23Related InformationCache and Tightly-Coupled Memoryldh / ldhioInstruction load halfword from memory or I/O peripheralOperationrB ←

Table 8-13: ldhBit Fields31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16A B IMM1615 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0IMM16 0x0fTable 8-14: ldhioBit F

ExceptionsSupervisor-only data addressMisaligned data addressTLB permission violation (read)Fast TLB miss (data)Double TLB miss (data)MPU region viola

DescriptionComputes the effective byte address specified by the sum of rAand the instruction's signed 16-bit immediate value. Loadsregister rB wi

Bit Fields15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0IMM16 0x37Related InformationCache and Tightly-Coupled MemorymovInstruction move register to registerOp

UsageThe maximum allowed value of IMMED is 65535. Theminimum allowed value is 0. To load a 32-bit constant into aregister, first load the upper 16 bit

Operation(2)N(3)Cycles Result Subnormal Rounding GCCInferencefloatis 250 4 int_to_float(a) NotapplicableNotapplicableCastingfixsi 249 2 float_to_int(a

Examplemovia r6, function_addressDescriptionWrites the address of label to rB.Pseudo-instructionmovia is implemented as:orhi rB, r0, %hiadj(label)addi

UsageCarry Detection (unsigned operands):Before or after the multiply operation, the carry out of the MSBof rC can be detected using the following ins

Bit FieldsA B C 0x2715 14 13 12 11 10 9 8 7 6 5 4 3 2 1 00x27 0 0x3amuliInstruction multiply immediateOperationrB ← (rA x σ(IMM16)) 31..0Assembler Sy

Assembler Syntaxmulxss rC, rA, rBExamplemulxss r6, r7, r8DescriptionTreating rA and rB as signed integers, mulxss multiplies rAtimes rB, and stores th

DescriptionTreating rA as a signed integer and rB as an unsigned integer,mulxsu multiplies rA times rB, and stores the 32 high-order bitsof the produc

UsageUse mulxuu and mul to compute the 64-bit product of two 32-bit unsigned integers. Furthermore, mulxuu can be used as partof the calculation of a

ExceptionsNoneInstruction TypeRInstruction FieldsC = Register index of operand rCBit Fields31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 160 0 C 0x1c15

Instruction FieldsA = Register index of operand rAB = Register index of operand rBC = Register index of operand rC31 30 29 28 27 26 25 24 23 22 21 20

DescriptionCalculates the bitwise logical OR of rA and (IMM16 : 0x0000)and stores the result in rB.ExceptionsNoneInstruction TypeIInstruction FieldsA

rdctlInstruction read from control registerOperationrC ← ctlNAssembler Syntaxrdctl rC, ctlNExamplerdctl r3, ctl31DescriptionReads the value contained

In Qsys, the Floating Point Hardware component is under Embedded Processors on the ComponentLibrary tab.The Nios II floating-point custom instructions

UsageThe previous register set is specified by status.PRS. By default,status.PRS indicates the register set in use before an exception,such as an exte

Bit Fields31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 160x1f 0 0 0x0515 14 13 12 11 10 9 8 7 6 5 4 3 2 1 00x05 0 0x3arolInstruction rotate leftOperat

DescriptionRotates rA left by the number of bits specified in IMM5 andstores the result in rC. The bits that shift out of the registerrotate into the

Bit Fields31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16A B C 0x0b15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 00x0b 0 0x3asllInstruction shift left logicalOp

DescriptionShifts rA left by the number of bits specified in IMM5(inserting zeroes), and then stores the result in rC.Usageslli performs the <<

Bit Fields31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16A B C 0x3b15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 00x3b 0 0x3asraiInstruction shift right arithme

Examplesrl r6, r7, r8DescriptionShifts rA right by the number of bits specified in rB4..0(inserting zeroes), and then stores the result in rC. Bits 31

Instruction FieldsA = Register index of operand rAC = Register index of operand rCIMM5 = 5-bit unsigned immediate valueBit Fields31 30 29 28 27 26 25

Instruction FieldsA = Register index of operand rAB = Register index of operand rBIMM16 = 16-bit signed immediate valueTable 8-19: stbBit Fields31 30

ExceptionsSupervisor-only data addressMisaligned data addressTLB permission violation (write)Fast TLB miss (data)Double TLB miss (data)MPU region viol

Signal Name Type Purposereset_req Reset This optional signal prevents the memory corruption by performing areset handshake before the processor resets

DescriptionComputes the effective byte address specified by the sum of rAand the instruction's signed 16-bit immediate value. Stores rBto the mem

subInstruction subtractOperationrC ← rA – rBAssembler Syntaxsub rC, rA, rBExamplesub r6, r7, r8DescriptionSubtract rB from rA and store the result in

UsageCarry Detection (unsigned operands):The carry bit indicates an unsigned overflow. Before or after asub operation, a carry out of the MSB can be d

Instruction FieldsA = Register index of operand rAB = Register index of operand rBC = Register index of operand rCBit Fields31 30 29 28 27 26 25 24 23

Instruction TypeRInstruction FieldsNoneBit Fields31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 160 0 0 0x3615 14 13 12 11 10 9 8 7 6 5 4 3 2 1 00x36 0

Bit Fields31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 160 0 0x1d 0x2d15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 00x2d IMM5 0x3awrctlInstruction write to con

UsageThe previous register set is specified by status.PRS. By default,status.PRS indicates the register set in use before an exception,such as an exte

Instruction FieldsA = Register index of operand rAB = Register index of operand rBC = Register index of operand rCBit Fields31 30 29 28 27 26 25 24 23

Assembler Syntaxxori rB, rA, IMM16Examplexori r6, r7, 100DescriptionCalculates the bitwise logical exclusive OR of rA and (0x0000 :IMM16) and stores t

Date Version ChangesOctober 2007 7.2.0 Added jmpi instruction.May 2007 7.1.0• Added table of contents to Introduction section.• Added Referenced Docum

An EIC can be software-configurable.Note: When the EIC interface and shadow register sets are implemented on the Nios II core, you mustensure that you

A Nios II core uses one or more of the following to provide memory and I/O access:• Instruction master port—An Avalon® Memory-Mapped (Avalon-MM) maste

Figure 2-2: Nios II Memory and I/O OrganizationSMemorySSlavePeripheralAvalon Master PortAvalon Slave PortMSMMTightly CoupledInstructionMemory NTightly

Supervisor Mode...3-1User M

Related InformationAvalon Interface SpecificationsRefer to the Avalon Interface Specifications for details of the Avalon-MM interface.Memory and Perip

operations can complete in a single clock cycle when the data master port is connected to zero-wait-statememory.The Nios II architecture supports on-c

Optimal cache configuration is application specific, although you can make decisions that are effectiveacross a range of applications. For example, if

Accessing Tightly-Coupled MemoryTightly-coupled memories occupy normal address space, the same as other memory devices connected viasystem interconnec

• Hardware translation lookaside buffers (TLBs), accelerating address translation• Separate TLBs for instruction and data accesses• Read, write, and e

Note: The Nios II MPU is optional and mutually exclusive from the Nios II MMU. Nios II systems caninclude either an MPU or MMU, but cannot include bot

Note: While the processor has no minimum clock frequency requirements, Altera recommends that yourdesign’s system clock frequency be at least four tim

Table 2-6: Trigger ActionsAction DescriptionBreak Halt execution and transfer control to the JTAG debug module.External trigger Assert a trigger signa

Execution vs. Data TraceThe JTAG debug module supports tracing the instruction bus (execution trace), the data bus (data trace),or both simultaneously

Date Version ChangesDecember 2010 10.1.0 Added reference to tightly-coupled memory tutorial.July 2010 10.0.0 Maintenance release.November 2009 9.1.0•

No-Operation Instruction... 3-65Potential Uni

Programming Model32015.04.02NII51003SubscribeSend FeedbackThis chapter describes the Nios® II programming model, covering processor features at the as

tion’s access to memory and peripherals. In systems with an MPU, your system software controls themode in which your application code runs. In Nios II

an MMU-based Nios II processor. Do not include an MMU in your Nios II system unless your operatingsystem requires it.Note: The Altera HAL and HAL-base

Whenever an instruction attempts to access a page that either has no TLB mapping, or lacks theappropriate permissions, the MMU generates an exception.

Physical Memory Address SpaceThe 4-GB physical memory is divided into low memory and high memory. The lowest ½ GB of physicaladdress space is low memo

Note: You can configure the number of TLB entries and the number of ways (set associativity) of the TLBwith the Nios II Processor parameter editor in

Related Information• Instantiating the Nios II Processor on page 4-1• Instantiating the Nios II Processor• Nios II Core Implementation Details on page

handle the exception as appropriate. The precise exception effectively prevents the illegal access tomemory.The MPU extends the Nios II processor to s

The region limit uses a less-than instead of a less-than-or-equal-to comparison because less-than providesa more efficient implementation. The limit i

General-Purpose RegistersThe Nios II architecture provides thirty-two 32-bit general-purpose registers, r0 through r31. Someregisters have names recog

Exception Handling...5-12ECC...

Control RegistersControl registers report the status and change the behavior of the processor. Control registers are accesseddifferently than the gene

Register Name Register Contents13 config Refer to The config Register on page 3-23Available only when the MPU or ECC is present.Otherwise reserved.14

Register Name Register Contents8 pteaddr Refer to The pteaddr RegisterAvailable only when the MMU is present. Otherwisereserved.9 tlbacc Refer to The

Table 3-9: status Control Register Field DescriptionsBit Description Access Reset AvailableRSIE RSIE is the register set interrupt-enable bit. When se

Bit Description Access Reset AvailableIL IL is the interrupt level field. The IL field controls whatlevel of external maskable interrupts can be servi

All fields in the estatus register have read/write access. All fields reset to 0.When the Nios II processor takes an interrupt, if status.eh is zero (

Related InformationException Processing on page 3-36The ipending RegisterThe value of the ipending register indicates the value of the enabled interru

Related Information• Instantiating the Nios II Processor on page 4-1• Instantiating the Nios II ProcessorThe pteaddr RegisterThe pteaddr register cont

Issuing a wrctl instruction to the tlbacc register writes the tlbacc register with the specified value. Iftlbmisc.WE = 1, the wrctl instruction also i

Bit FieldsReserved EE WAY RD WE PID15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0PID DBL BAD PERM DTable 3-19: tlbmisc Control Register Field DescriptionsField

ABI for Linux Systems...7-

When system software changes the fields that specify the TLB entry, there is no immediate effect onpteaddr.VPN, tlbmisc.PID, or the tlbacc register. T

Refer to Nios II Exceptions (In Decreasing Priority Order) table in the "Exception Overview" section formore information on these exceptions

Table 3-21: badaddr Control Register Field DescriptionsField Description Access Reset AvailableBADDR BADDR contains the byte instruction address or da

Field Description Access Reset AvailableECCEXE ECCEX is the ECC error exception enable bit. WhenECCEXE = 1, the Nios II processor generates ECC errore

The INDEX and D fields specify the region information to access when an MPU region read or writeoperation is performed. The D field specifies whether

Field Description Access Reset AvailablePERM PERM specifies the access permissions for the region. Read/Write0 Only with MPURD RD is the read region f

MASK Encoding Region Size0x1FFFC00 64 KB0x1FFF800 128 KB0x1FFF000 256 KB0x1FFE000 512 KB0x1FFC000 1 MB0x1FF8000 2 MB0x1FF0000 4 MB0x1FE0000 8 MB0x1FC0

The MT FlagThe MT flag determines the default memory type of an MPU data region. . The MT flag only applies to dataregions. For instruction regions, t

The WR FlagSetting the WR flag signifies that an MPU region write operation should be performed when a wrctlinstruction is issued to the mpuacc regist

When shadow register sets are implemented, status.CRS indicates the register set currently in use. ANios II core can have up to 63 shadow register set

cmpgtu ...8-2

Bit Description Access Reset AvailableRSIE RSIE is the register set interrupt-enable bit. When set to 1, this bitallows the processor to serviceextern

• If the processor is currently running in the normal register set, insert the new register set number inestatus.CRS, and execute eret.• If the proces

MPU region write operations set new values for the attributes of a region. Each MPU region writeoperation consists of the following actions:• Execute

Working with ECCEnabling ECCThe ECC is disabled on system reset. Before enabling the ECC, initialize the Nios II RAM blocks to avoidspurious ECC error

Instruction Cache Tag RAM1. Ensure all code up to the JMP instruction is in the same instruction cache line or is located in anITCM.2. Use a FLUSHI in

Exception ProcessingException processing is the act of responding to an exception, and then returning, if possible, to the pre-exception execution sta

The following table columns specify information for the exceptions:• Exception—Gives the name of the exception.• Type—Specifies the exception type.• A

Exception Type Available Cause Address VectorSupervisor-onlyinstructionInstruction-relatedMMU orMPU10 ea–4(15)General exceptionTrap instruction Instru

Exception Type Available Cause Address VectorMPU regionviolation (data)Instruction-relatedMPU 17 badaddr (dataaddress)General exceptionRelated Informa

The reset state is undefined for all other system components, including but not limited to:• General-purpose registers, except for zero (r0) in the no

rol ...

Understanding Register UsageThe bstatus control register and general-purpose registers bt (r25) and ba (r30) in the normal registerset are reserved fo

• Requested Register Set on page 3-42• Requested Interrupt Level on page 3-42Requested Handler AddressThe RHA specifies the address of the handler ass

For the best interrupt performance, assign a dedicated register set to each of the most time-criticalinterrupts. Less-critical interrupts can share re

Figure 3-2: Relationship Between ienable, ipending, PIE and Hardware InterruptsIPENDING0IPENDING1IPENDING2ipending RegisterIPENDING31irq0irq1irq2irq31

• Fast TLB miss• Double TLB miss• TLB permission violation• MPU region violationNote: All noninterrupt exception handlers must run in the normal regis

Note: All undefined opcodes are reserved. The processor does occasionally use some undefinedencodings internally. Executing one of these undefined opc

A data address is considered misaligned if the byte address is not a multiple of the width of the load orstore instruction data width (four bytes for

There are two kinds of fast TLB miss exceptions:• Fast TLB miss (instruction)—Any instruction fetch can cause this exception.• Fast TLB miss (data)—Lo

There are two kinds of MPU region violation exceptions:• MPU region violation (instruction)—Any instruction fetch can cause this exception.• MPU regio

• RHA—The requested handler address for the interrupt handler assigned to the requested interrupt.• RRS—The requested register set to be used when the

Introduction12015.04.02NII51001SubscribeSend FeedbackThis handbook describes the Nios® II Classic processor from a high-level conceptual description t

Exception Flow with the Internal Interrupt ControllerA general exception handler determines which of the pending interrupts has the highest priority,

Processor Status Registeror FieldSystem Status Before Taking ExceptionExternal Interrupt Asserted (18)Internal Interrupt Asserted or Noninterrupt Exce

Determining the Cause of Interrupt and Instruction-Related ExceptionsThe general exception handler must determine the cause of each exception and then

handle division error exception else if (instruction is signed divide and numerator == 0x80000000

Nested Exceptions with an External Interrupt ControllerWith an EIC, handling of nested interrupts is more sophisticated than with the internal interru

Multiple interrupts can share a register set, with some loss of performance. There are two techniques forsharing register sets:• Set status.RSIE to 0.

The status.IL field controls what level of external maskable interrupts can be serviced. The processorservices a maskable interrupt only if its reques

Note: When the EIC interface and shadow register sets are implemented on the Nios II core, you mustensure that your software, including ISRs, is built

The Nios II architecture provides the following mechanisms to bypass the cache:• When no MMU is present, bit 31 of the address is reserved for bit-31

For example, in a 64-KB direct-mapped cache with a 16-byte line, bits 15:4 are used to select the line.Assume that virtual address 0x1000 is mapped to