Altera PHY IP Core Uživatelská příručka

101 Innovation DriveSan Jose, CA 95134www.altera.com EMI_DDR3_UG-2.1 Section II. DDR3 SDRAM Controller with ALTMEMPHY IPUser GuideExternal Memory Inte

1–4 Chapter 1: About This IPFeaturesExternal Memory Interface Handbook Volume 3 December 2010 Altera CorporationSection II. DDR3 SDRAM Controller with

6–6 Chapter 6: Functional Description—High-Performance ControllerBlock DescriptionExternal Memory Interface Handbook Volume 3 December 2010 Altera Cor

Chapter 6: Functional Description—High-Performance Controller 6–7Block DescriptionDecember 2010 Altera Corporation External Memory Interface Handbook

6–8 Chapter 6: Functional Description—High-Performance ControllerBlock DescriptionExternal Memory Interface Handbook Volume 3 December 2010 Altera Cor

Chapter 6: Functional Description—High-Performance Controller 6–9Block DescriptionDecember 2010 Altera Corporation External Memory Interface Handbook

6–10 Chapter 6: Functional Description—High-Performance ControllerBlock DescriptionExternal Memory Interface Handbook Volume 3 December 2010 Altera Co

Chapter 6: Functional Description—High-Performance Controller 6–11Block DescriptionDecember 2010 Altera Corporation External Memory Interface Handbook

6–12 Chapter 6: Functional Description—High-Performance ControllerBlock DescriptionExternal Memory Interface Handbook Volume 3 December 2010 Altera Co

Chapter 6: Functional Description—High-Performance Controller 6–13Block DescriptionDecember 2010 Altera Corporation External Memory Interface Handbook

6–14 Chapter 6: Functional Description—High-Performance ControllerExample Top-Level FileExternal Memory Interface Handbook Volume 3 December 2010 Alte

Chapter 6: Functional Description—High-Performance Controller 6–15Example Top-Level FileDecember 2010 Altera Corporation External Memory Interface Han

Chapter 1: About This IP 1–5Unsupported FeaturesDecember 2010 Altera Corporation External Memory Interface Handbook Volume 3Section II. DDR3 SDRAM Con

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Chapter 6: Functional Description—High-Performance Controller 6–17Top-level Signals DescriptionDecember 2010 Altera Corporation External Memory Interf

6–18 Chapter 6: Functional Description—High-Performance ControllerTop-level Signals DescriptionExternal Memory Interface Handbook Volume 3 December 20

Chapter 6: Functional Description—High-Performance Controller 6–19Top-level Signals DescriptionDecember 2010 Altera Corporation External Memory Interf

6–20 Chapter 6: Functional Description—High-Performance ControllerTop-level Signals DescriptionExternal Memory Interface Handbook Volume 3 December 20

Chapter 6: Functional Description—High-Performance Controller 6–21Top-level Signals DescriptionDecember 2010 Altera Corporation External Memory Interf

6–22 Chapter 6: Functional Description—High-Performance ControllerTop-level Signals DescriptionExternal Memory Interface Handbook Volume 3 December 20

December 2010 Altera Corporation External Memory Interface Handbook Volume 3Section II. DDR3 SDRAM Controller with ALTMEMPHY IP User Guide7. Functiona

7–2 Chapter 7: Functional Description—High-Performance Controller IIBlock DescriptionExternal Memory Interface Handbook Volume 3 December 2010 Altera

Chapter 7: Functional Description—High-Performance Controller II 7–3Block DescriptionDecember 2010 Altera Corporation External Memory Interface Handbo

1–6 Chapter 1: About This IPResource UtilizationExternal Memory Interface Handbook Volume 3 December 2010 Altera CorporationSection II. DDR3 SDRAM Con

7–4 Chapter 7: Functional Description—High-Performance Controller IIBlock DescriptionExternal Memory Interface Handbook Volume 3 December 2010 Altera

Chapter 7: Functional Description—High-Performance Controller II 7–5Block DescriptionDecember 2010 Altera Corporation External Memory Interface Handbo

7–6 Chapter 7: Functional Description—High-Performance Controller IIBlock DescriptionExternal Memory Interface Handbook Volume 3 December 2010 Altera

Chapter 7: Functional Description—High-Performance Controller II 7–7Block DescriptionDecember 2010 Altera Corporation External Memory Interface Handbo

7–8 Chapter 7: Functional Description—High-Performance Controller IIBlock DescriptionExternal Memory Interface Handbook Volume 3 December 2010 Altera

Chapter 7: Functional Description—High-Performance Controller II 7–9Block DescriptionDecember 2010 Altera Corporation External Memory Interface Handbo

7–10 Chapter 7: Functional Description—High-Performance Controller IIExample Top-Level FileExternal Memory Interface Handbook Volume 3 December 2010 A

Chapter 7: Functional Description—High-Performance Controller II 7–11Example Top-Level FileDecember 2010 Altera Corporation External Memory Interface

7–12 Chapter 7: Functional Description—High-Performance Controller IITop-level Signals DescriptionExternal Memory Interface Handbook Volume 3 December

Chapter 7: Functional Description—High-Performance Controller II 7–13Top-level Signals DescriptionDecember 2010 Altera Corporation External Memory Int

Chapter 1: About This IP 1–7Resource UtilizationDecember 2010 Altera Corporation External Memory Interface Handbook Volume 3Section II. DDR3 SDRAM Con

7–14 Chapter 7: Functional Description—High-Performance Controller IITop-level Signals DescriptionExternal Memory Interface Handbook Volume 3 December

Chapter 7: Functional Description—High-Performance Controller II 7–15Top-level Signals DescriptionDecember 2010 Altera Corporation External Memory Int

7–16 Chapter 7: Functional Description—High-Performance Controller IITop-level Signals DescriptionExternal Memory Interface Handbook Volume 3 December

Chapter 7: Functional Description—High-Performance Controller II 7–17Top-level Signals DescriptionDecember 2010 Altera Corporation External Memory Int

7–18 Chapter 7: Functional Description—High-Performance Controller IIRegister Maps DescriptionExternal Memory Interface Handbook Volume 3 December 201

Chapter 7: Functional Description—High-Performance Controller II 7–19Register Maps DescriptionDecember 2010 Altera Corporation External Memory Interfa

7–20 Chapter 7: Functional Description—High-Performance Controller IIRegister Maps DescriptionExternal Memory Interface Handbook Volume 3 December 201

Chapter 7: Functional Description—High-Performance Controller II 7–21Register Maps DescriptionDecember 2010 Altera Corporation External Memory Interfa

7–22 Chapter 7: Functional Description—High-Performance Controller IIRegister Maps DescriptionExternal Memory Interface Handbook Volume 3 December 201

Chapter 7: Functional Description—High-Performance Controller II 7–23Register Maps DescriptionDecember 2010 Altera Corporation External Memory Interfa

1–8 Chapter 1: About This IPSystem RequirementsExternal Memory Interface Handbook Volume 3 December 2010 Altera CorporationSection II. DDR3 SDRAM Cont

7–24 Chapter 7: Functional Description—High-Performance Controller IIRegister Maps DescriptionExternal Memory Interface Handbook Volume 3 December 201

Chapter 7: Functional Description—High-Performance Controller II 7–25Register Maps DescriptionDecember 2010 Altera Corporation External Memory Interfa

7–26 Chapter 7: Functional Description—High-Performance Controller IIRegister Maps DescriptionExternal Memory Interface Handbook Volume 3 December 201

December 2010 Altera Corporation External Memory Interface Handbook Volume 3Section II. DDR3 SDRAM Controller with ALTMEMPHY IP User Guide8. LatencyLa

8–2 Chapter 8: LatencyExternal Memory Interface Handbook Volume 3 December 2010 Altera CorporationSection II. DDR3 SDRAM Controller with ALTMEMPHY IP

Chapter 8: Latency 8–3December 2010 Altera Corporation External Memory Interface Handbook Volume 3Section II. DDR3 SDRAM Controller with ALTMEMPHY IP

8–4 Chapter 8: LatencyExternal Memory Interface Handbook Volume 3 December 2010 Altera CorporationSection II. DDR3 SDRAM Controller with ALTMEMPHY IP

December 2010 Altera Corporation External Memory Interface Handbook Volume 3Section II. DDR3 SDRAM Controller with ALTMEMPHY IP User Guide9. Timing Di

9–2 Chapter 9: Timing DiagramsDDR3 High-Performance ControllersExternal Memory Interface Handbook Volume 3 December 2010 Altera CorporationSection II.

Chapter 9: Timing Diagrams 9–3DDR3 High-Performance ControllersDecember 2010 Altera Corporation External Memory Interface Handbook Volume 3Section II.

Chapter 1: About This IP 1–9Installation and LicensingDecember 2010 Altera Corporation External Memory Interface Handbook Volume 3Section II. DDR3 SDR

9–4 Chapter 9: Timing DiagramsDDR3 High-Performance ControllersExternal Memory Interface Handbook Volume 3 December 2010 Altera CorporationSection II.

Chapter 9: Timing Diagrams 9–5DDR3 High-Performance ControllersDecember 2010 Altera Corporation External Memory Interface Handbook Volume 3Section II.

9–6 Chapter 9: Timing DiagramsDDR3 High-Performance ControllersExternal Memory Interface Handbook Volume 3 December 2010 Altera CorporationSection II.

Chapter 9: Timing Diagrams 9–7DDR3 High-Performance ControllersDecember 2010 Altera Corporation External Memory Interface Handbook Volume 3Section II.

9–8 Chapter 9: Timing DiagramsDDR3 High-Performance ControllersExternal Memory Interface Handbook Volume 3 December 2010 Altera CorporationSection II.

Chapter 9: Timing Diagrams 9–9DDR3 High-Performance ControllersDecember 2010 Altera Corporation External Memory Interface Handbook Volume 3Section II.

9–10 Chapter 9: Timing DiagramsDDR3 High-Performance ControllersExternal Memory Interface Handbook Volume 3 December 2010 Altera CorporationSection II

Chapter 9: Timing Diagrams 9–11DDR3 High-Performance ControllersDecember 2010 Altera Corporation External Memory Interface Handbook Volume 3Section II

9–12 Chapter 9: Timing DiagramsDDR3 High-Performance ControllersExternal Memory Interface Handbook Volume 3 December 2010 Altera CorporationSection II

Chapter 9: Timing Diagrams 9–13DDR3 High-Performance Controllers IIDecember 2010 Altera Corporation External Memory Interface Handbook Volume 3Section

1–10 Chapter 1: About This IPInstallation and LicensingExternal Memory Interface Handbook Volume 3 December 2010 Altera CorporationSection II. DDR3 SD

9–14 Chapter 9: Timing DiagramsDDR3 High-Performance Controllers IIExternal Memory Interface Handbook Volume 3 December 2010 Altera CorporationSection

Chapter 9: Timing Diagrams 9–15DDR3 High-Performance Controllers IIDecember 2010 Altera Corporation External Memory Interface Handbook Volume 3Section

9–16 Chapter 9: Timing DiagramsDDR3 High-Performance Controllers IIExternal Memory Interface Handbook Volume 3 December 2010 Altera CorporationSection

Chapter 9: Timing Diagrams 9–17DDR3 High-Performance Controllers IIDecember 2010 Altera Corporation External Memory Interface Handbook Volume 3Section

9–18 Chapter 9: Timing DiagramsDDR3 High-Performance Controllers IIExternal Memory Interface Handbook Volume 3 December 2010 Altera CorporationSection

Chapter 9: Timing Diagrams 9–19DDR3 High-Performance Controllers IIDecember 2010 Altera Corporation External Memory Interface Handbook Volume 3Section

9–20 Chapter 9: Timing DiagramsDDR3 High-Performance Controllers IIExternal Memory Interface Handbook Volume 3 December 2010 Altera CorporationSection

Chapter 9: Timing Diagrams 9–21DDR3 High-Performance Controllers IIDecember 2010 Altera Corporation External Memory Interface Handbook Volume 3Section

9–22 Chapter 9: Timing DiagramsDDR3 High-Performance Controllers IIExternal Memory Interface Handbook Volume 3 December 2010 Altera CorporationSection

Chapter 9: Timing Diagrams 9–23DDR3 High-Performance Controllers IIDecember 2010 Altera Corporation External Memory Interface Handbook Volume 3Section

December 2010 Altera Corporation External Memory Interface Handbook Volume 3Section II. DDR3 SDRAM Controller with ALTMEMPHY IP User Guide2. Getting S

9–24 Chapter 9: Timing DiagramsDDR3 High-Performance Controllers IIExternal Memory Interface Handbook Volume 3 December 2010 Altera CorporationSection

Chapter 9: Timing Diagrams 9–25DDR3 High-Performance Controllers IIDecember 2010 Altera Corporation External Memory Interface Handbook Volume 3Section

9–26 Chapter 9: Timing DiagramsDDR3 High-Performance Controllers IIExternal Memory Interface Handbook Volume 3 December 2010 Altera CorporationSection

Chapter 9: Timing Diagrams 9–27DDR3 High-Performance Controllers IIDecember 2010 Altera Corporation External Memory Interface Handbook Volume 3Section

9–28 Chapter 9: Timing DiagramsDDR3 High-Performance Controllers IIExternal Memory Interface Handbook Volume 3 December 2010 Altera CorporationSection

December 2010 Altera Corporation External Memory Interface Handbook Volume 3Section II. DDR3 SDRAM Controller with ALTMEMPHY IP User GuideAdditional I

Info–2 Chapter :Typographic ConventionsExternal Memory Interface Handbook Volume 3 December 2010 Altera CorporationSection II. DDR3 SDRAM Controller w

2–2 Chapter 2: Getting StartedSOPC Builder FlowExternal Memory Interface Handbook Volume 3 December 2010 Altera CorporationSection II. DDR3 SDRAM Cont

Chapter 2: Getting Started 2–3SOPC Builder FlowDecember 2010 Altera Corporation External Memory Interface Handbook Volume 3Section II. DDR3 SDRAM Cont

External Memory Interface Handbook Volume 3 December 2010 Altera CorporationSection II. DDR3 SDRAM Controller with ALTMEMPHY IP User Guide© 2010 Alter

2–4 Chapter 2: Getting StartedMegaWizard Plug-In Manager FlowExternal Memory Interface Handbook Volume 3 December 2010 Altera CorporationSection II. D

Chapter 2: Getting Started 2–5MegaWizard Plug-In Manager FlowDecember 2010 Altera Corporation External Memory Interface Handbook Volume 3Section II. D

2–6 Chapter 2: Getting StartedGenerated FilesExternal Memory Interface Handbook Volume 3 December 2010 Altera CorporationSection II. DDR3 SDRAM Contro

Chapter 2: Getting Started 2–7Generated FilesDecember 2010 Altera Corporation External Memory Interface Handbook Volume 3Section II. DDR3 SDRAM Contro

2–8 Chapter 2: Getting StartedGenerated FilesExternal Memory Interface Handbook Volume 3 December 2010 Altera CorporationSection II. DDR3 SDRAM Contro

Chapter 2: Getting Started 2–9Generated FilesDecember 2010 Altera Corporation External Memory Interface Handbook Volume 3Section II. DDR3 SDRAM Contro

2–10 Chapter 2: Getting StartedHardCopy Device Migration GuidelinesExternal Memory Interface Handbook Volume 3 December 2010 Altera CorporationSection

Chapter 2: Getting Started 2–11HardCopy Device Migration GuidelinesDecember 2010 Altera Corporation External Memory Interface Handbook Volume 3Section

2–12 Chapter 2: Getting StartedHardCopy Device Migration GuidelinesExternal Memory Interface Handbook Volume 3 December 2010 Altera CorporationSection

December 2010 Altera Corporation External Memory Interface Handbook Volume 3Section II. DDR3 SDRAM Controller with ALTMEMPHY IP User Guide3. Parameter

December 2010 Altera Corporation External Memory Interface Handbook Volume 3Section II. DDR3 SDRAM Controller with ALTMEMPHY IP User GuideContentsChap

3–2 Chapter 3: Parameter SettingsALTMEMPHY Parameter SettingsExternal Memory Interface Handbook Volume 3 December 2010 Altera CorporationSection II. D

Chapter 3: Parameter Settings 3–3ALTMEMPHY Parameter SettingsDecember 2010 Altera Corporation External Memory Interface Handbook Volume 3Section II. D

3–4 Chapter 3: Parameter SettingsALTMEMPHY Parameter SettingsExternal Memory Interface Handbook Volume 3 December 2010 Altera CorporationSection II. D

Chapter 3: Parameter Settings 3–5ALTMEMPHY Parameter SettingsDecember 2010 Altera Corporation External Memory Interface Handbook Volume 3Section II. D

3–6 Chapter 3: Parameter SettingsALTMEMPHY Parameter SettingsExternal Memory Interface Handbook Volume 3 December 2010 Altera CorporationSection II. D

Chapter 3: Parameter Settings 3–7ALTMEMPHY Parameter SettingsDecember 2010 Altera Corporation External Memory Interface Handbook Volume 3Section II. D

3–8 Chapter 3: Parameter SettingsALTMEMPHY Parameter SettingsExternal Memory Interface Handbook Volume 3 December 2010 Altera CorporationSection II. D

Chapter 3: Parameter Settings 3–9ALTMEMPHY Parameter SettingsDecember 2010 Altera Corporation External Memory Interface Handbook Volume 3Section II. D

3–10 Chapter 3: Parameter SettingsALTMEMPHY Parameter SettingsExternal Memory Interface Handbook Volume 3 December 2010 Altera CorporationSection II.

Chapter 3: Parameter Settings 3–11ALTMEMPHY Parameter SettingsDecember 2010 Altera Corporation External Memory Interface Handbook Volume 3Section II.

iv ContentsExternal Memory Interface Handbook Volume 3 December 2010 Altera CorporationSection II. DDR3 SDRAM Controller with ALTMEMPHY IP User GuideS

3–12 Chapter 3: Parameter SettingsALTMEMPHY Parameter SettingsExternal Memory Interface Handbook Volume 3 December 2010 Altera CorporationSection II.

Chapter 3: Parameter Settings 3–13DDR3 SDRAM Controller with ALTMEMPHY Parameter SettingsDecember 2010 Altera Corporation External Memory Interface Ha

3–14 Chapter 3: Parameter SettingsDDR3 SDRAM Controller with ALTMEMPHY Parameter SettingsExternal Memory Interface Handbook Volume 3 December 2010 Alt

Chapter 3: Parameter Settings 3–15DDR3 SDRAM Controller with ALTMEMPHY Parameter SettingsDecember 2010 Altera Corporation External Memory Interface Ha

3–16 Chapter 3: Parameter SettingsDDR3 SDRAM Controller with ALTMEMPHY Parameter SettingsExternal Memory Interface Handbook Volume 3 December 2010 Alt

Chapter 3: Parameter Settings 3–17DDR3 SDRAM Controller with ALTMEMPHY Parameter SettingsDecember 2010 Altera Corporation External Memory Interface Ha

3–18 Chapter 3: Parameter SettingsDDR3 SDRAM Controller with ALTMEMPHY Parameter SettingsExternal Memory Interface Handbook Volume 3 December 2010 Alt

December 2010 Altera Corporation External Memory Interface Handbook Volume 3Section II. DDR3 SDRAM Controller with ALTMEMPHY IP User Guide4. Compiling

4–2 Chapter 4: Compiling and SimulatingCompiling the DesignExternal Memory Interface Handbook Volume 3 December 2010 Altera CorporationSection II. DDR

Chapter 4: Compiling and Simulating 4–3Compiling the DesignDecember 2010 Altera Corporation External Memory Interface Handbook Volume 3Section II. DDR

Contents vDecember 2010 Altera Corporation External Memory Interface Handbook Volume 3Section II. DDR3 SDRAM Controller with ALTMEMPHY IP User GuideCo

4–4 Chapter 4: Compiling and SimulatingSimulating the DesignExternal Memory Interface Handbook Volume 3 December 2010 Altera CorporationSection II. DD

Chapter 4: Compiling and Simulating 4–5Simulating the DesignDecember 2010 Altera Corporation External Memory Interface Handbook Volume 3Section II. DD

4–6 Chapter 4: Compiling and SimulatingSimulating the DesignExternal Memory Interface Handbook Volume 3 December 2010 Altera CorporationSection II. DD

December 2010 Altera Corporation External Memory Interface Handbook Volume 3Section II. DDR3 SDRAM Controller with ALTMEMPHY IP User Guide5. Functiona

5–2 Chapter 5: Functional Description—ALTMEMPHYBlock DescriptionExternal Memory Interface Handbook Volume 3 December 2010 Altera CorporationSection II

Chapter 5: Functional Description—ALTMEMPHY 5–3Block DescriptionDecember 2010 Altera Corporation External Memory Interface Handbook Volume 3Section II

5–4 Chapter 5: Functional Description—ALTMEMPHYBlock DescriptionExternal Memory Interface Handbook Volume 3 December 2010 Altera CorporationSection II

Chapter 5: Functional Description—ALTMEMPHY 5–5Block DescriptionDecember 2010 Altera Corporation External Memory Interface Handbook Volume 3Section II

5–6 Chapter 5: Functional Description—ALTMEMPHYBlock DescriptionExternal Memory Interface Handbook Volume 3 December 2010 Altera CorporationSection II

Chapter 5: Functional Description—ALTMEMPHY 5–7Block DescriptionDecember 2010 Altera Corporation External Memory Interface Handbook Volume 3Section II

vi ContentsExternal Memory Interface Handbook Volume 3 December 2010 Altera CorporationSection II. DDR3 SDRAM Controller with ALTMEMPHY IP User GuideH

5–8 Chapter 5: Functional Description—ALTMEMPHYBlock DescriptionExternal Memory Interface Handbook Volume 3 December 2010 Altera CorporationSection II

Chapter 5: Functional Description—ALTMEMPHY 5–9Block DescriptionDecember 2010 Altera Corporation External Memory Interface Handbook Volume 3Section II

5–10 Chapter 5: Functional Description—ALTMEMPHYBlock DescriptionExternal Memory Interface Handbook Volume 3 December 2010 Altera CorporationSection I

Chapter 5: Functional Description—ALTMEMPHY 5–11Block DescriptionDecember 2010 Altera Corporation External Memory Interface Handbook Volume 3Section I

5–12 Chapter 5: Functional Description—ALTMEMPHYBlock DescriptionExternal Memory Interface Handbook Volume 3 December 2010 Altera CorporationSection I

Chapter 5: Functional Description—ALTMEMPHY 5–13Block DescriptionDecember 2010 Altera Corporation External Memory Interface Handbook Volume 3Section I

5–14 Chapter 5: Functional Description—ALTMEMPHYBlock DescriptionExternal Memory Interface Handbook Volume 3 December 2010 Altera CorporationSection I

Chapter 5: Functional Description—ALTMEMPHY 5–15Block DescriptionDecember 2010 Altera Corporation External Memory Interface Handbook Volume 3Section I

5–16 Chapter 5: Functional Description—ALTMEMPHYBlock DescriptionExternal Memory Interface Handbook Volume 3 December 2010 Altera CorporationSection I

Chapter 5: Functional Description—ALTMEMPHY 5–17Block DescriptionDecember 2010 Altera Corporation External Memory Interface Handbook Volume 3Section I

December 2010 Altera Corporation External Memory Interface Handbook Volume 3Section II. DDR3 SDRAM Controller with ALTMEMPHY IP User Guide1. About Thi

5–18 Chapter 5: Functional Description—ALTMEMPHYBlock DescriptionExternal Memory Interface Handbook Volume 3 December 2010 Altera CorporationSection I

Chapter 5: Functional Description—ALTMEMPHY 5–19Block DescriptionDecember 2010 Altera Corporation External Memory Interface Handbook Volume 3Section I

5–20 Chapter 5: Functional Description—ALTMEMPHYBlock DescriptionExternal Memory Interface Handbook Volume 3 December 2010 Altera CorporationSection I

Chapter 5: Functional Description—ALTMEMPHY 5–21Block DescriptionDecember 2010 Altera Corporation External Memory Interface Handbook Volume 3Section I

5–22 Chapter 5: Functional Description—ALTMEMPHYBlock DescriptionExternal Memory Interface Handbook Volume 3 December 2010 Altera CorporationSection I

Chapter 5: Functional Description—ALTMEMPHY 5–23ALTMEMPHY SignalsDecember 2010 Altera Corporation External Memory Interface Handbook Volume 3Section I

5–24 Chapter 5: Functional Description—ALTMEMPHYALTMEMPHY SignalsExternal Memory Interface Handbook Volume 3 December 2010 Altera CorporationSection I

Chapter 5: Functional Description—ALTMEMPHY 5–25ALTMEMPHY SignalsDecember 2010 Altera Corporation External Memory Interface Handbook Volume 3Section I

5–26 Chapter 5: Functional Description—ALTMEMPHYALTMEMPHY SignalsExternal Memory Interface Handbook Volume 3 December 2010 Altera CorporationSection I

Chapter 5: Functional Description—ALTMEMPHY 5–27ALTMEMPHY SignalsDecember 2010 Altera Corporation External Memory Interface Handbook Volume 3Section I

1–2 Chapter 1: About This IPRelease InformationExternal Memory Interface Handbook Volume 3 December 2010 Altera CorporationSection II. DDR3 SDRAM Cont

5–28 Chapter 5: Functional Description—ALTMEMPHYALTMEMPHY SignalsExternal Memory Interface Handbook Volume 3 December 2010 Altera CorporationSection I

Chapter 5: Functional Description—ALTMEMPHY 5–29ALTMEMPHY SignalsDecember 2010 Altera Corporation External Memory Interface Handbook Volume 3Section I

5–30 Chapter 5: Functional Description—ALTMEMPHYALTMEMPHY SignalsExternal Memory Interface Handbook Volume 3 December 2010 Altera CorporationSection I

Chapter 5: Functional Description—ALTMEMPHY 5–31PHY-to-Controller InterfacesDecember 2010 Altera Corporation External Memory Interface Handbook Volume

5–32 Chapter 5: Functional Description—ALTMEMPHYPHY-to-Controller InterfacesExternal Memory Interface Handbook Volume 3 December 2010 Altera Corporati

Chapter 5: Functional Description—ALTMEMPHY 5–33PHY-to-Controller InterfacesDecember 2010 Altera Corporation External Memory Interface Handbook Volume

5–34 Chapter 5: Functional Description—ALTMEMPHYPHY-to-Controller InterfacesExternal Memory Interface Handbook Volume 3 December 2010 Altera Corporati

Chapter 5: Functional Description—ALTMEMPHY 5–35PHY-to-Controller InterfacesDecember 2010 Altera Corporation External Memory Interface Handbook Volume

5–36 Chapter 5: Functional Description—ALTMEMPHYPHY-to-Controller InterfacesExternal Memory Interface Handbook Volume 3 December 2010 Altera Corporati

Chapter 5: Functional Description—ALTMEMPHY 5–37PHY-to-Controller InterfacesDecember 2010 Altera Corporation External Memory Interface Handbook Volume

Chapter 1: About This IP 1–3FeaturesDecember 2010 Altera Corporation External Memory Interface Handbook Volume 3Section II. DDR3 SDRAM Controller with

5–38 Chapter 5: Functional Description—ALTMEMPHYUsing a Custom ControllerExternal Memory Interface Handbook Volume 3 December 2010 Altera CorporationS

Chapter 5: Functional Description—ALTMEMPHY 5–39Using a Custom ControllerDecember 2010 Altera Corporation External Memory Interface Handbook Volume 3S

5–40 Chapter 5: Functional Description—ALTMEMPHYUsing a Custom ControllerExternal Memory Interface Handbook Volume 3 December 2010 Altera CorporationS

Chapter 5: Functional Description—ALTMEMPHY 5–41Using a Custom ControllerDecember 2010 Altera Corporation External Memory Interface Handbook Volume 3S

5–42 Chapter 5: Functional Description—ALTMEMPHYUsing a Custom ControllerExternal Memory Interface Handbook Volume 3 December 2010 Altera CorporationS

December 2010 Altera Corporation External Memory Interface Handbook Volume 3Section II. DDR3 SDRAM Controller with ALTMEMPHY IP User Guide6. Functiona

6–2 Chapter 6: Functional Description—High-Performance ControllerBlock DescriptionExternal Memory Interface Handbook Volume 3 December 2010 Altera Cor

Chapter 6: Functional Description—High-Performance Controller 6–3Block DescriptionDecember 2010 Altera Corporation External Memory Interface Handbook

6–4 Chapter 6: Functional Description—High-Performance ControllerBlock DescriptionExternal Memory Interface Handbook Volume 3 December 2010 Altera Cor

Chapter 6: Functional Description—High-Performance Controller 6–5Block DescriptionDecember 2010 Altera Corporation External Memory Interface Handbook