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Altera Temperature Sensor IP Core User Guide
2015.05.04
UG-01074
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The Altera Temperature Sensor IP core configures the temperature sensing diode (TSD) block to utilize
the temperature measurement feature in the FPGA.
Note: Beginning from the Quartus II software version 14.0, the name of this IP core has been changed
from ALTTEMP_SENSE to Altera Temperature Sensor IP core.
Related Information
Introduction to Altera IP Cores
Provides general information about Altera IP cores.
Altera Temperature Sensor Features
The following table lists the Altera Temperature Sensor IP core features.
Table 1: Altera Temperature Sensor Features
Device Features
Stratix
®
V, Stratix IV, Arria
®
V, and Arria
V GZ
An internal TSD with built-in 8-bit analog-to-digital
converter (ADC) circuitry to monitor die temperature
A clock divider to reduce the frequency of the clock signal
to 1 MHz or less before clocking the ADC
An asynchronous clear signal to reset the TSD block
Arria 10
An internal TSD with built-in 10-bit ADC circuitry
clocked by 1 MHz internal oscillator to monitor die
temperature
Does not require external clock source
An asynchronous clear signal to reset the TSD block
Note: The Altera Temperature Sensor IP core does not have simulation model files and cannot be
simulated.
©
2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are
trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance
of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any
products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information,
product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device
specifications before relying on any published information and before placing orders for products or services.
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Strany 1 - Device Features

Altera Temperature Sensor IP Core User Guide2015.05.04UG-01074SubscribeSend FeedbackThe Altera Temperature Sensor IP core configures the temperature s

Strany 2

Value of tsdcalo[7:0] in Hexadecimal Temperature in Degree Celsius (°C)... ...6C -20... ...62 -30... ...4E -50... ...3A -70° CAltera Temperature Senso

Strany 3 - 2015.05.04

Date DocumentVersionChanges MadeJune 2013 3.1• Updated the “Temperature Sensing Operation” on page 3–1 toclarify that enabling the ADC allows you to m

Strany 4 - Option Value

Altera Temperature Sensor Functional DescriptionTemperature Sensing Operation for Arria 10 DevicesFigure 1: Altera Temperature Sensor IP Core Top-Leve

Strany 5 - Using Clear Box Generator

Temperature Sensing Operation for Arria V, Arria V GZ, Stratix IV, and Stratix VDevicesFigure 2: Altera Temperature Sensor Block DiagramThis figure sh

Strany 6

Note: When you choose not to create the clr port , the Altera Temperature Sensor IP core connects theclr port to GND. In this case, you must reset the

Strany 7

Figure 3: Complete Design FileThis figure shows the complete design file.INPUTVCCclrINPUTVCCclkINPUTVCCceclrclkcetsd_s4inst1OUTPUTtsdcalo[7..0]OUTPUTt

Strany 8

Note: Ensure that you enclose String-type values with double-quotes.2. Access the command prompt of your operating system, and change the current dire

Strany 9

This table lists the parameter editor and CLI parameter settings for the Altera Temperature Sensor IPcore.Table 3: Altera Temperature Sensor IP core P

Strany 10 - Document Revision History

Parameter CLI ParameterDescriptionName LegalValuesName LegalValuesCreate anasynchronousclear portOn/Off clr — Specifies whether to turn onthe asynchro

Strany 11 - Changes Made

Signals Direction Width (Bit) Descriptionclr Input 1 The asynchronous clear signal. When you assert theclr signal, the IP core sets the tsdcalo[7:0] s

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