Altera Stratix II GX EP2SGX90 Transceiver Signal Integrit Uživatelský manuál stáhnout pdf (Strana 9)

Altera Corporation Reference Manual 1–3

May 2006 Stratix II GX EP2SGX90 Transceiver Signal Integrity Development Board

Introduction

Block Diagram

Figure 1–1 shows a functional block diagram of the Stratix II GX

EP2SGX90 transceiver signal integrity development board.

Figure 1–1. Stratix II GX EP2SGX90 Transceiver Signal Integrity Development

Board Block Diagram

Target Applications

The board is used for the following applications:

■ Demonstrating key StratixIIGX device features

■ Device qualification, e.g., jitter, pre-emphasis, equalization, and

signal integrity testing, as well as receiver sensitivity.

■ De-coupling Quartus

II software, transceiver architecture, and

Altera MegaWizard

Plug-In Manager demonstrations (supporting

devices and interfaces included)

■ Demonstrating Stratix II GX device transceiver features

■ Characterization testing of high-speed serial interfaces

■ Interoperability testing between various devices via on-board SMA

connectors

■ Power supply evaluation (on-board regulation and banana jack

options)

Power Supply

Management Block

with Switching &

Linear Regulators

Thermal

Management

Block

Active Serial

Configuration Using

EPCS64 Device

JTAG

Configuration

SMA

Connectors

for High-Speed

Interfaces

Clock

Management

Unit

USB

Interface

Debugging

Header

General

User

Interfac

Block

FPGA

Configuation

Block

LEDs

7-Segment Displays

Flash Memory

Stratix II GX

Device

Push Buttons

DIP Switches

1 2 3 4 5 6 7 8 9 10 11 12 13 14 ... 39 40

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