Altera Stratix II GX Embedded Gigabit Ethernet MAC/PHY Uživatelský manuál stáhnout pdf (Strana 17)

Stratix II GX Embedded Gigabit Ethernet MAC / PHY

User's Guide

Version 1.0 - October 2005

Figure 6: VQM Netlist Generation

The VQM Netlist (embedded_gige_mac_phy.vqm) is created in the directory quartus/

atom_netlists.

Note: Without the free license from Altera, the VQM netlist cannot be generated and an error

message will appear. You can disregard this message as it will not prevent you from running RTL

simulation.

3.9 Full Timing Gate Level Simulation

The gate level verification is performed using Quartus II VHDL output files (Structural VHDL and

SDF timing files) in the directory quartus/simulation.

To run the gate level simulation with Modelsim, use as described in chapters “

3.5” and following. A

gate level simulation when the Testbuilder simulation option “Run Gate-Level” is used.

With a Modelsim PE or Modelsim AE, run the script gate.do:

• do gate.do

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Altera Stratix II GX Embedded Gigabit Ethernet MAC/PHY Uživatelský manuál Strana 17