Altera Nios Development Board Stratix II Edition Uživatelský manuál stáhnout pdf (Strana 24)

2–14 Reference Manual Altera Corporation

Nios Development Board Stratix II Edition May 2007

Board Components

Y24 94 Byte Enable 0 enet_be_n0

Y23 95 Byte Enable 1 enet_be_n1

AA24 96 Byte Enable 2 enet_be_n2

AA23 97 Byte Enable 3 enet_be_n3

Y26 31 Read enet_ior_n

Y25 32 Write enet_iow_n

U26 78 Address Line fe_a1

U25 79 Address Line fe_a2

T25 80 Address Line fe_a3

T24 81 Address Line fe_a4

V20 82 Address Line fe_a5

V19 83 Address Line fe_a6

U20 84 Address Line fe_a7

U19 85 Address Line fe_a8

T22 86 Address Line fe_a9

T21 87 Address Line fe_a10

T20 88 Address Line fe_a11

T19 89 Address Line fe_a12

U22 90 Address Line fe_a13

U21 91 Address Line fe_a14

V22 92 Address Line fe_a15

D15 107 Data Line fe_d0

G15 106 Data Line fe_d1

E19 105 Data Line fe_d2

D20 104 Data Line fe_d3

G19 102 Data Line fe_d4

D19 101 Data Line fe_d5

E20 100 Data Line fe_d6

F20 99 Data Line fe_d7

M20 76 Data Line fe_d8

M19 75 Data Line fe_d9

N20 74 Data Line fe_d10

N19 73 Data Line fe_d11

N22 71 Data Line fe_d12

Table 2–9. Ethernet MAC/PHY Pin Table (Continued)

FPGA Pin U4 Pin Pin Function Board Net Name (1)

1 2 ... 19 20 21 22 23 24 25 26 27 28 29 ... 61 62

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Altera Nios Development Board Stratix II Edition Uživatelský manuál Strana 24