Altera MAX 10 Clocking and PLL Uživatelský manuál Strana 35
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MAX 10 Clocking and PLL Design
Considerations
3
2015.05.04
UG-M10CLKPLL
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Clock Networks Design Considerations
Guideline: Clock Enable Signals
Altera recommends using the clkena signals when switching the clock source to the PLLs or GCLK. The
recommended sequence is as follows:
1. Disable the primary output clock by deasserting the clkena signal.
2. Switch to the secondary clock using the dynamic select signals of the clock control block.
3. Allow some clock cycles of the secondary clock to pass before reasserting the clkena signal. The exact
number of clock cycles to wait before enabling the secondary clock depends on your design. You can
build a custom logic to ensure a glitch-free transition when switching between different clock sources.
Related Information
• Clock Enable Signals on page 2-7
• ALTCLKCTRL Parameters on page 5-1
• ALTCLKCTRL Ports and Signals on page 5-2
Guideline: Connectivity Restrictions
The following guidelines describe the restrictions associated with the signal sources that can drive the
inclk input:
• You must use the inclk ports that are consistent with the clkselect ports.
• When you are using multiple input sources, the inclk ports can only be driven by the dedicated clock
input pins and the PLL clock outputs.
• If the clock control block feeds any inclk port of another clock control block, both clock control
blocks must be able to be reduced to a single clock control block of equivalent functionality.
• When you are using the glitch-free switchover feature, the clock you are switching from must be active.
If the clock is not active, the switchover circuit cannot transition from the clock you originally selected.
©
2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are
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trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance
of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any
products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information,
product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device
specifications before relying on any published information and before placing orders for products or services.
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101 Innovation Drive, San Jose, CA 95134
- 101 Innovation Drive 1
- San Jose, CA 95134 1
- Contents 2
- Altera Corporation 3
- Clock Networks Overview 5
- Internal Oscillator Overview 5
- PLLs Overview 5
- • PLL cascading 6
- • Reference clock switchover 6
- Features 7
- Clock Resources 8
- Global Clock Network Sources 8
- Pin GCLK 9
- Global Clock Control Block 10
- Input Description 11
- Related Information 12
- Clock Enable Signals 13
- PLL Architecture 14
- UG-M10CLKPLL 15
- 2015.05.04 15
- PLL Features 16
- PLL Locations 16
- Clock Pin to PLL Connections 18
- PLL Control Signals 19
- Clock Feedback Modes 20
- Source Synchronous Mode 21
- No Compensation Mode 21
- Normal Mode 22
- PLL External Clock Output 23
- ADC Clock Input from PLL 25
- Spread-Spectrum Clocking 25
- PLL Programmable Parameters 25
- Programmable Phase Shift 26
- Clock Switchover 28
- Manual Clock Switchover 31
- PLL Cascading 32
- PLL Reconfiguration 32
- Considerations 35
- PLLs Design Considerations 36
- Guideline: PLL Cascading 37
- Guideline: Clock Switchover 37
- ALTCLKCTRL IP Core 39
- Search for installed IP cores 40
- ALTPLL IP Core 43
- Block Name 50
- Number of Bits 50
- Counter Control Bit Total 50
- 3. Ignore this directory 55
- ALTPLL_RECONFIG IP Core 56
- Internal Oscillator IP Core 59
- ALTCLKCTRL IP Core References 64
- ALTCLKCTRL Ports and Signals 65
- ALTPLL IP Core References 67
- Parameter Value Description 68
- ALTPLL Ports and Signals 72
- Port Name 73
- Condition Description 73
- ALTPLL_RECONFIG Parameters 77
- Parameter Value Decription 85
- Date Version Changes 86
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