Altera Data Conversion HSMC Uživatelský manuál stáhnout pdf (Strana 12)

2–6 Chapter 2: Board Components and Interfaces

Clocks

Data Conversion HSMC Reference Manual © November 2008 Altera Corporation

External Clock Output Select Jumper (J23)

Table 2–8 lists the external clock output select jumper (J23) settings.

Clocks

This section describes the external clock input and output SMA connectors.

External Clock Input SMA Connectors (J26, J30)

The CLK SMA connector (J26 or J30) provides an external clock input. It can be

selected to be the input to U1, U2, and U3 (Figure 2–3). An external clock input

provides (while using a particular design) the flexibility to use the same external clock

source for the entire system under test. If you choose to use a single-ended clock, R112

must be removed and R111 be installed.

Table 2–8. External Clock Output Select Jumper (J23) Settings

Clock Source Board Reference

Schematic Signal Name

(1)

External Clock Output Select

Jumper (J23) Settings

FPGA Clock HSMC Connector FPGA_CLK_A_P

FPGA_CLK_A_N

Pins 3 and 5

Pins 4 and 6

FPGA Clock HSMC Connector FPGA_CLK_B_P

FPGA_CLK_B_N

Pins 1 and 3

Pins 4 and 6

A/D A DCO A/D Channel A ADA_DCO_P

ADA_DCO_N

Pins 3 and 5

Pins 2 and 4

A/D B DCO A/D Channel B ADB_DCO_P

ADB_DCO_N

Pins 1 and 3

Pins 2 and 4

Note to Table 2–8:

(1) On the schematic, MUX (U13) output signal names are RX_CLK_P and RX_CLK_N.

Figure 2–3. External Clock Input Schematic

External Clock In

J26 LTI-SASF54GT

XT_CK_IN_N

J30

XT_CK_IN_P

R75

Unipolar

XT_CK_IN_UNI

R111

R112

Bipolar

XT_CK_IN_BI

TT1_8_KK91

VTT_XCK

XT_IN_P

1.00K, 1%

XT_IN_N

1.00K, 1%

3.3 V

R78

C70

0.1µF

LTI-SASF54GT

1 2 ... 7 8 9 10 11 12 13 14 15 16 17 ... 43 44

Komentáře k této Příručce

Žádné komentáře

Altera Data Conversion HSMC Uživatelský manuál Strana 12

Komentáře k této Příručce

Související produkty a manuály pro Měřící nástroje Altera Data Conversion HSMC